ML9489.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 ML9489 데이타시트 다운로드

No Preview Available !

ML9489
Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 160 Outputs LCD Driver
FEDL9489-02
Issue Date: Apr. 3, 2013
GENERAL DESCRIPTION
The ML9489 is an LCD driver LSI, consists of a 160-bit shift register, a 640-bit data latch, 160 sets of LCD
drivers, and a common signal generation circuit.
It can directly drive an LCD up to 160 segments for static display, 320 segments for 1/2-duty display, 480
segments for 1/3-duty display, and 640 segments for 1/4-duty display.
The three-wire serial interface and I2C interface are selectable.
FEATURES
Logic power supply voltage : 2.7 to 5.5 V
LCD drive power supply voltage : 4.5 to 5.5 V
Maximum number of segments
Static display
: 160 segments
1/2-duty display
: 320 segments
1/3-duty display
: 480 segments
1/4-duty display
: 640 segments
Interface with microcomputer :
Serial interface : DATA, CLOCK, LOAD
CLOCK transfer speed up to 1 MHz
I2C interface : SDA, SCL, SDAACK
SCL transfer speed up to 400 kHz
Built-in CR oscillator circuit using the internal resistor or External resistor
Cascade connectable (up to eight chips)
Built-in common signal generation circuit
Built-in common output intermediate-value voltage generation circuit
Built-in POC (Power On Clear) circuit
Gold bump chip (ML9489DVWA)
Comparison table
Item ML
9479EDVWA
ML9489DVWA
Frame Frequency
65Hz/75Hz/85Hz/95Hz
130Hz/150Hz/170Hz/190Hz
(Internal oscillation) (programmable)
(programmable)
1/32
http://www.Datasheet4U.com

No Preview Available !

FEDL9489-02
ML9489
BLOCK DIAGRAM
VLCD
SEG1
BIAS
Bias
Resi.
SEG160
160-Dot Segment Driver
Duty0
Duty1
M/S
160-Ch Data Selector
160
160-Bit
Latch4
160
160-Bit
Latch3
160
160-Bit
Latch2
160
160-Bit
Latch1
I2C
LOAD
DATA (SDA)
CLOCK (SCL)
SDAACK
SA0
A1
A0
OSC I/E
OSC1
OSCR
OSC2
CKO
POCEB
RESETB
TEST1
TEST2
VDD
GND
Latch
Selector
Command
Decoder
OSC
POC
160
160-bit Shift Register
Timing
Generator
COMON
Driver
COM1
COM2
COM3
COM4
SYNCB
2/32

No Preview Available !

FEDL9489-02
ML9489
ABSOLUTE MAXIMUM RATINGS
Item
Logic power supply voltage
LCD drive power supply voltage
Input voltage
Output short-circuit current
Chip temperature
Storage temperature
Symbol
VDD
VLCD
VI
Is
Tc —
TSTG
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
— -55
Rating
-0.3 to 6.0
-0.3 to 6.0
– 0.3 to VDD + 0.3
-2.0 to +2.0
125 °C
to +150
Unit
V
V
V
mA
°C
Note: Do not use the ML9489 by short-circuiting one output pin to another output pin as well as to other pin
(input pin, input/output pin, or power supply pin).
RECOMMENDED OPERATION CONDITIONS
Item
Logic power supply voltage
LCD drive power supply voltage
OSC IN clock frequency
Data clock frequency
SCL clock frequency
Operating temperature
Symbol
VDD*
VLCD*
fCP1
fCP2
fSCL
Ta
Condition
Range
2.7 to 5.5
4.5 to 5.5
up to 10
up to 1.0
up to 400
-40 to +105
Note(*): Use at VDD VLCD.
The relation between OSC IN clock frequency and frame frequency is as the equation below.
fFRM = fOSC /24
Unit
V
V
kHz
MHz
kHz
°C
Recommended setting range for external component (oscillator circuit)
Item
Oscillation resistor
Frame frequency
Symbol
Rf
fFRM
Condition
(F1,F0)=(0,1)
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= –40 to +105°C)
Min T
YP
Max
Unit
423 470 517
k
47 75 114 Hz
The relation between oscillation resistor and frame frequency is as the equation below.
fFRM = fOSC /(8 x 24)
fosc = 1 / (Device coefficient x External resistor Rf)
Device coefficient = 73.8 x 10-12 ± 25%
3/32

No Preview Available !

FEDL9489-02
ML9489
ELECTRICAL CHARACTERISTICS
DC Characteristics
Item
"H" input voltage
"L" input voltage
Input leakage current 1
Input leakage current 2
Pull-up current
"H" output voltage
"L" output voltage 1
"L" output voltage 2
Driver
Segment
ON resistor Common
Symbol
VIH
VIL
IL1
IL2
Ipu
VOH
VOL1
VOL2
VOHS
VOHC
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= -40 to +105°C)
Condition
Min. T yp. Max. Unit Applicable pin
— 0.8V
— GND
VI = VDD or 0 V
VI = VDD or 0V
POCEB="H"
DD
-1.0 —
-1.0
—V
DD V
0.2VDD
1.0
— 1.0
(*1)
V (*1)
μA (*1)
μA RESET B
VDD = 5.0V,VI = 0 V
POCEB = "L"
30
— 140
μA RESET B
IO = -600μA
IO = 600μA —
IO = 600μA —
0.9VDD
——
0.1VDD
0.1VDD
VCKO, SYNCB
V CKO, SYNCB
V SDAACK
VLCD = 5V
—5
15 kSEG1 to SEG160
VLCD = 5V
—5
12 kCOM 1 to COM4
(*1) : DATA(SDA), CLOCK(SCL), LOAD, M/S, SYNCB, Duty1, Duty0, BIAS, SA0, A1, A0, OSC1, OSC I/E,
I2C, POCEB
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= -40 to +105°C)
Item Symbol
Condition
Min. Typ.
Max. U
nit
Applicable
pin
Static supply
IDDS
VDD=VLCD=5.5 V
Input pin fixed to "H" or "L"
—8
15 μA VDD
current
ILCDS
Oscillation stopped, output no-load
POCEB="L"
—9
15 μA VLCD
Dynamic supply
current 1
IDD1
ILCD1
VDD=VLCD= 5.5 V (*2)(*3)
Clock OSC1 external input
fCP1=1.8kHz
(*6)
(*7)
— 12
— 11
22 μA VDD
19 μA VLCD
Dynamic supply
current 2
IDD2
ILCD2
VDD=VLCD= 5.5 V (*2)(*3)
Internal oscillation
(*6)
(*7)
— 67
— 11
94 μA VDD
19 μA VLCD
Dynamic supply
current 3
IDD3
ILCD3
VDD=VLCD= 5.5 V (*2)(*4)(*6)
Internal oscillation
At three-wire serial IF data input
— 202
— 11
304 μA VDD
19 μA VLCD
Dynamic supply
current 4
IDD4
ILCD4
VDD=VLCD= 5.5 V (*2)(*5)(*6)
Internal oscillation
At I2C IF data input
— 232
— 11
354 μA VDD
19 μA VLCD
(*2) : M/S = "H", 1/4-duty, 1/3-bias, (F1,F0) = (1,1) 190 Hz, POCEB = "L", output pin no-load.
(*3) : Three-wire serial or I2C interface. Input pin fixed to "H" or "L".
(*4) : Serial interface, data input frequency = 1 MHz.
(*5) : I2C interface, data input frequency = 400 kHz.
(*6) : Alternately inputs "0" and "1" for LCD display data (checkered display).
(*7) : Inputs all "1s" for LCD display data (all illuminated).
4/32

No Preview Available !

FEDL9489-02
ML9489
Switching Characteristics
OSC timing
Item
OSC IN clock frequency
(external input)
Clock pulse width
(External input)
Clock rise and fall time
(external input)
External Rf clock
frequency
(Internal oscillation)
Internal clock frequency
(Internal oscillation)
Symbol
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min. Typ. Max. U nit Applicable pin
fCP1
Clock input from OSC1.
tWCP1 40 OSC2 and OSCR open.
OSC I/E = "L"
tOSC
— 1.8
10
——
— — (*1)
kHz OSC1
μs O SC1
μs O SC1
Between OSC1 and OSC2
fOSC1
Rf = 470k
(F1,F0)=(0,1)
OSCR open.
18 28.8 44 kHz OSC1 , OSC2
OSC I/E = "H"
OSC1 open.
fOSC2
(F1,F0)=(0,1)
OSC2 and OSCR short-circuited.
18
28.8
44
kHz
OSC1, OSCR,
OSC2
OSC I/E = "H"
The relation between OSC IN clock frequency and frame frequency is as the equation below.
fFRM = fOSC /24
(*1) tOSC is a reference value.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=2μs.
Serial interface timing
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Item
Symbol
Condition
Min. Typ. Max. Unit Applicable pin
Data clock frequency
fCP2
— — 1 MHz CLOCK
Data clock pulse width
tWCP2
100 — — ns CLOCK
Data setup time
tSU
50 — — ns DATA
Data hold time
tHD
50 — — ns CLOCK
CLOCK-LOAD timing
tCL
100 — — ns CLOCK
LOAD-CLOCK timing
tLC
100 — — ns LOAD
LOAD pulse width
tWLD
100 — — ns LOAD
Signal rise and fall time tsr,tsf
——
(*2)
ns
CLOCK,DATA,
LOAD
(*2) tsr and tsf shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=10ns.
5/32