AD9625.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 AD9625 데이타시트 다운로드

No Preview Available !

Data Sheet
12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS,
1.3 V/2.5 V Analog-to-Digital Converter
AD9625
FEATURES
12-bit 2.5 GSPS ADC, no missing codes
SFDR = 79 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS
Differential analog input: 1.2 V p-p
Differential clock input
3.2 GHz analog input bandwidth, full power
High speed 6- or 8-lane JESD204B serial output at 2.6 GSPS
Subclass 1: 6.5 Gbps at 2.6 GSPS
Two independent decimate by 8 or decimate by 16 filters
with 10-bit NCOs
Supply voltages: 1.3 V, 2.5 V
Serial port control
Flexible digital output modes
Built-in selectable digital test patterns
Timestamp feature
Conversion error rate < 10−15
APPLICATIONS
Spectrum analyzers
Military communications
Radar
High performance digital storage oscilloscopes
Active jamming/antijamming
Electronic surveillance and countermeasures
GENERAL DESCRIPTION
The AD9625 is a 12-bit monolithic sampling analog-to-digital
converter (ADC) that operates at conversion rates of up to
2.6 giga samples per second (GSPS). This product is designed
for sampling wide bandwidth analog signals up to the second
Nyquist zone. The combination of wide input bandwidth, high
sampling rate, and excellent linearity of the AD9625 is ideally
suited for spectrum analyzers, data acquisition systems, and a
wide assortment of military electronics applications, such as
radar and electronic countermeasures.
The analog input, clock, and SYSREF± signals are differential
inputs. The JESD204B-based high speed serialized output is
configurable in a variety of one-, two-, four-, six-, or eight-lane
configurations. The product is specified over the industrial
temperature range of −40°C to +85°C, measured at the case.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD DRGND
VCM
VIN+
VIN–
RBIAS_EXT
REFERENCE
ADC
CORE
DIGITAL INTERFACE
AND CONTROL
DDC
fS/8 OR fS/16
CONTROL
REGISTERS
SYSREF±
CLK±
CLOCK
MANAGEMENT
AD9625
CMOS DIGITAL
INPUT/OUTPUT
CMOS
DIGITAL
INPUT/
OUTPUT
LVDS
DIGITAL
INPUT/
OUTPUT
SERDOUT[0]±
SERDOUT[1]±
SERDOUT[2]±
SERDOUT[3]±
SERDOUT[4]±
SERDOUT[5]±
SERDOUT[6]±
SERDOUT[7]±
FD
RSTB
IRQ
SYNCINB±
DIVCLK±
SDIO SCLK CSB
Figure 1.
PRODUCT HIGHLIGHTS
1. High performance: exceptional SFDR in high sample rate
applications, direct RF sampling, and on-chip reference.
2. Flexible digital data output formats based on the JESD204B
specification.
3. Control path SPI interface port that supports various
product features and functions, such as data formatting,
gain, and offset calibration values.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

No Preview Available !

AD9625
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 3 
Specifications..................................................................................... 4 
DC Specifications ......................................................................... 4 
AC Specifications.......................................................................... 5 
Digital Specifications ................................................................... 6 
Switching Specifications .............................................................. 7 
Timing Specifications .................................................................. 7 
Absolute Maximum Ratings............................................................ 9 
Thermal Characteristics .............................................................. 9 
ESD Caution.................................................................................. 9 
Pin Configuration and Function Descriptions........................... 10 
Typical Performance Characteristics ........................................... 16 
AD9625-2.0 ................................................................................. 17 
AD9625-2.5 ................................................................................. 20 
AD9625-2.6 ................................................................................. 24 
Equivalent Test Circuits ................................................................. 27 
Theory of Operation ...................................................................... 28 
ADC Architecture ...................................................................... 28 
Fast Detect ................................................................................... 28 
Gain Threshold Operation........................................................ 28 
Test Modes................................................................................... 29 
Analog Input Considerations........................................................ 30 
Differential Input Configurations ............................................ 30 
Using the ADA4961 ................................................................... 30 
DC Coupling ............................................................................... 32 
Clock Input Considerations ...................................................... 32 
Digital Downconverters (DDC) ................................................... 33 
Frequency Synthesizer and Mixer ............................................ 33 
Data Sheet
Numerically Controlled Oscillator .......................................... 33 
High Bandwidth Decimator ..................................................... 33 
Low Bandwidth Decimator....................................................... 36 
Digital Outputs ............................................................................... 37 
Introduction to the JESD204B Interface ................................. 37 
Functional Overview ................................................................. 37 
JESD204B Link Establishment ................................................. 39 
Physical Layer Output................................................................ 43 
Scrambler..................................................................................... 43 
Tail Bits ........................................................................................ 43 
DDC Modes (Single and Dual) ................................................ 43 
CheckSum ................................................................................... 44 
8-Bit/10-Bit Encoder Control ................................................... 44 
Initial Lane Alignment Sequence (ILAS)................................ 44 
Lane Synchronization ................................................................ 45 
JESD204B Application Layers .................................................. 48 
Frame Alignment Character Insertion.................................... 51 
Thermal Considerations............................................................ 51 
Power Supply Considerations................................................... 51 
Serial Port Interface (SPI).............................................................. 52 
Configuration Using the SPI..................................................... 52 
Hardware Interface..................................................................... 52 
Memory Map .................................................................................. 53 
Reading the Memory Map Register ......................................... 53 
Memory Map Registers ............................................................. 53 
Applications Information .............................................................. 71 
Design Guidelines ...................................................................... 71 
Power and Ground Recommendations ................................... 71 
Clock Stability Considerations ................................................. 71 
SPI Port ........................................................................................ 71 
Outline Dimensions ....................................................................... 72 
Ordering Guide .......................................................................... 72 
Rev. C | Page 2 of 72

No Preview Available !

Data Sheet
REVISION HISTORY
9/2016—Rev. B to Rev. C
Changes to ADC Output Control Bits on JESD204B Samples
Section ..............................................................................................45
Changes to Table 94 ........................................................................67
Changes to Table 110 and Table 111.............................................69
Changes to Table 113 and Table 114.............................................70
Changes to the Clock Stability Considerations Section .............71
Changes to Ordering Guide...........................................................72
5/2015—Rev. A to Rev. B
Added AD9625-2.6 ....................................................... Throughout
Change to Figure 1 ............................................................................1
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................5
Change to Figure 5 ..........................................................................10
Added Endnote 1, Table 8 ..............................................................11
Added Endnote 2, Table 9 ..............................................................13
Added AD9625-2.6 Section ...........................................................24
Changes to Figure 61 and Figure 63 .............................................27
Changes to Table 11 ........................................................................30
Added Using the ADA4961 Section .............................................30
Added Figure 77; Renumbered Sequentially, Figure 78,
Figure 79, and Figure 80 .................................................................31
Changes to Table 12 ........................................................................34
Changes to Low Bandwidth Decimator Section and Table 13.....36
Changes to Table 28 ........................................................................54
Changes to Table 107 ......................................................................69
Changes to Ordering Guide...........................................................72
9/2014—Rev. 0 to Rev. A
Added AD9625-2.5 ....................................................... Throughout
Changes to Features and General Description Sections ..............1
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................5
Changes to Table 3 ............................................................................6
Changes to Table 4 ............................................................................7
Changes to Figure 3 and Figure 4....................................................8
Changes to Table 6 ............................................................................9
Changes to Pin K4; Figure 5, Table 8, and Table 9......................10
Added Typical Performance Characteristics Summary and
Changes to Typical Performance Characteristics .......................16
AD9625
Changes to Figure 45, Figure 49, and Figure 50; Added
Figure 51 to Figure 54.....................................................................23
Changes to Gain Threshold Operation Section..........................24
Changes to Analog Input Considerations Section......................26
Changes to Digital Downconverters (DDC) Section .................28
Added Figure 68 ..............................................................................32
Changes to Data Streaming Section; Added Link Setup
Parameters Section..........................................................................33
Changes to Digital Outputs, Timing, and Controls Section and
Table 15.............................................................................................34
Changes to Table 16 and Table 17.................................................35
Added Table 18 ................................................................................36
Added Multichip Synchronization Using SYSREF± Timestamp,
Six Lane Output Mode, and SYSREF± Setup and Hold IRQ
Sections.............................................................................................39
Added IRQ Guardband Delays (SYSREF± Setup and Hold)
Section ..............................................................................................40
Added Using Rising/Falling Edges of CLK to Latch SYSREF±
Section ..............................................................................................41
Changes to Configuration Using the SPI Section.......................46
Changes to Transfer Register Map Section, Table 26, and
Table 27.............................................................................................47
Changes to Table 28, Table 29, and Table 30 ...............................48
Changes to Table 33 and Table 34.................................................49
Changes to Table 53 ........................................................................52
Changes to Table 54 ........................................................................52
Changes to Table 58 ........................................................................54
Changes to Table 71 ........................................................................56
Changes to Table 79 and Table 80.................................................57
Changes to Table 81, Table 82, Table 83, Table 84, Table 85, and
Table 86.............................................................................................58
Changes to Table 89 ........................................................................59
Changes to Table 92 and Table 93.................................................60
Changes to Table 94, Table 97, and Table 98 ...............................61
Changes to Table 101 and Table 106.............................................62
Added Table 107 and Table 108.....................................................63
Added Table 115 and Table 116.....................................................64
Added Applications Information Section....................................65
Changes to Ordering Guide...........................................................66
5/2014—Revision 0: Initial Version
Rev. C | Page 3 of 72

No Preview Available !

AD9625
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal
reference, AIN = −1.0 dBFS, default SPI settings, dc-coupled output data, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity
(DNL)
Integral Nonlinearity (INL)
ANALOG INPUTS
Differential Input
Voltage Range
Resistance
Capacitance
Internal Common-Mode
Voltage (VCM)
Analog Full-Power
Bandwidth2
Input Referred Noise
POWER SUPPLIES
AVDD1
AVDD2
DRVDD1
DRVDD2
DVDD1
DVDD2
DVDDIO
SPI_VDDIO
IAVDD1
IAVDD2
IDRVDD1
IDRVDD2
IDVDD1
IDVDD2
IDVDDIO
ISPI_VDDIO
Power Dissipation
Power-Down Dissipation
Test Conditions/
Comments
Temperature1
AD9625-2.0
Min Typ Max
12
AD9625-2.5
Min Typ Max
12
AD9625-2.6
Min Typ Max
12
Unit
Bits
Full
Guaranteed
Guaranteed
Guaranteed
Full
−7 ±0.5 +6.4 −7
±0.5 +6.4 −8.5 ±0.5 +7.0 LSB
Full
−8
+8 −10.8
+14.2 −13.8
+20.9 %FSR
Full −0.7 ±0.3 +0.7 −0.5 ±0.3 +0.7 −0.6 ±0.3 +0.7 LSB
Full −3.6 ±0.9 +3.6 −2.1 ±1.0 +2.1 −2.7 ±1.0 +2.3 LSB
Internal VREF = 1.2 V
Full
25°C
25°C
Full
Internal termination 25°C
25°C
Eight lane mode
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.1 1
1 V p-p
100 100
100 Ω
1.5 1.5
1.5 pF
492 525 563 492 525 563 492 525 563 mV
3.2 3.2
22
3.2 GHz
2 LSBRMS
1.26 1.3 1.32 1.26
2.4 2.5 2.6 2.4
1.26 1.3 1.32 1.26
2.4 2.5 2.6 2.4
1.26 1.3 1.32 1.26
2.4 2.5 2.6 2.4
2.4 2.5 3.3 2.4
2.4 2.5 3.3 2.4
1120 1222
383 460
456 470
9 10
410 430
<1
<1
<1
3.48 3.8
125 3.8
1.3
2.5
1.3
2.5
1.3
2.5
2.5
2.5
1250
427
476
9
425
<1
<1
<1
3.90
125
1.32
2.6
1.32
2.6
1.32
2.6
3.3
3.3
1351
491
518
10
473
4.2
1.26
2.4
1.26
2.4
1.26
2.4
2.4
2.4
1.3
2.5
1.3
2.5
1.3
2.5
2.5
2.5
1267
432
497
9
441
<1
<1
<1
4.0
125
1.32
2.6
1.32
2.6
1.32
2.6
3.3
3.3
1390
492
544
10
503
4.3
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
W
mW
1 Full temperature range is −40°C to +85°C measured at the case (TC).
2 See Figure 75 and Figure 76 for networks.
Rev. C | Page 4 of 72

No Preview Available !

Data Sheet
AD9625
AC SPECIFICATIONS
AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling, 1.2 V internal reference,
AIN = −1.0 dBFS, sample clock input = 1.65 V p-p differential, default SPI settings, unless otherwise noted.
Table 2.
Parameter
SPEED GRADE
ANALOG INPUT
NOISE DENSITY
SIGNAL-TO-NOISE RATIO
(SNR)
fIN = 100 MHz
fIN = 500 MHz
fIN = 1000 MHz
fIN = 1800 MHz
SIGNAL-TO-NOISE AND
DISTORTION (SINAD)
fIN = 100 MHz
fIN = 500 MHz
fIN = 1000 MHz
fIN = 1800 MHz
EFFECTIVE NUMBER OF
BITS (ENOB)
fIN = 100 MHz
fIN = 500 MHz
fIN = 1000 MHz
fIN = 1800 MHz
SPURIOUS FREE
DYNAMIC RANGE
(SFDR)
fIN = 100 MHz
fIN = 500 MHz
fIN = 1000 MHz
fIN = 1800 MHz
WORST OTHER SPUR
fIN = 100 MHz
fIN = 500 MHz
fIN = 1000 MHz
fIN = 1800 MHz
TWO-TONE
INTERMODULATION
DISTORTION (IMD)
fIN1 = 728.5 MHz, fIN2 =
731.5 MHz
fIN1 = 1805.5 MHz, fIN2 =
1808.5 MHz
Test Conditions/
Comments
Full scale
Including second or
thrid harmonic
Excluding second or
third harmonic
At −7 dBFS per tone
Temperature1
Full
25°C
AD9625-2.0
Min Typ Max
2.0
1.1
−149.0
AD9625-2.5
Min Typ Max
2.5
1.2
−149.5
AD9625-2.6
Min Typ Max
2.6
1.1
−150.0
Unit
GSPS
V p-p
dBFS/Hz
25°C 59.5 58.3 58.1 dBFS
25°C 59.4 58.0 58.0 dBFS
25°C 59.0 57.6 57.5 dBFS
Full
55.4 58.2
54.1 57.0
55.0 56.6
dBFS
25°C 58.4 57.2 57.0 dBc
25°C 58.4 57.0 56.9 dBc
25°C 58.0 56.5 56.4 dBc
Full
54.1 57.2
53.1 55.9
53.9 55.6
dBc
25°C 9.4 9.2 9.2 Bits
25°C 9.4 9.2 9.2 Bits
25°C 9.3 9.1 9.1 Bits
25°C 9.2 9.0 8.9 Bits
25°C
25°C
25°C
Full
80
81
80
67 76
77
76
79
70 77
80.5
79.6
77.3
65 75.4
dBc
dBc
dBc
dBc
25°C −80 −77 −81 dBc
25°C −86 −76 −83 dBc
25°C −83 −82 −80 dBc
Full
−85 −73
−78 −70
−78.0 −66.0 dBc
25°C
−82.8
−81.2
−78.3
dBc
25°C
−77.6
−76.3
−77.7
dBc
1 Full temperature range is −40°C to +85°C measured at the case (TC).
Rev. C | Page 5 of 72