ISL6353.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 ISL6353 데이타시트 다운로드

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Multiphase PWM Regulator for VR12 DDR Memory
Systems
ISL6353
The ISL6353 is a three-phase PWM buck regulator controller for
VR12 DDR memory applications. The multi-phase implementation
results in better system performance, superior thermal
management, lower component cost and smaller PCB area.
The ISL6353 has two integrated power MOSFET drivers for
implementing a cost effective and space saving power
management solution.
The PWM modulator of theISL6353 is based on Intersil’s Robust
Ripple Regulator™ (R3) technology. Compared with the traditional
multi-phase buck regulator, the R3 modulator commands variable
PWM switching frequency during load transients,achieving faster
transientresponse.R3 also naturally goes into pulse frequency
modulation operation in light load conditions to achieve higher light
load efficiency.
The ISL6353 is designedto be completely compliant with VR12
specifications. The ISL6353has a serial VID (SVID) bus
communicating with the CPU. The output can be programmed for
1-, 2- or 3-phase inet rleaved operation.The output voltage and
power state can also be controlled independent of the serial VID
bus.
The ISL6353 has several other key features. It supports DCR
current sensing with a single NTC thermistor for DCR
temperature compensation or accurate resistor current sensing.
It also has remote voltage sense, adjustable switching frequency,
current monitor, OC/OV protection and power-good. Temperature
monitor and thermal alert is available too.
Features
• VR12 Serial Communications Bus
• Precision Voltage Regulation
- 5mV Steps with VID Fast/Slow Slew Rates
• Supports Two Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Programmable 1, 2 or 3-Phase Operation
• Adaptive Body Diode Conduction Time Reduction
• Superior Noise Immunity and Transient Response
• Pin Programmable Output Voltage and Power State Mode
• Output Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable Switching Frequency
• Resistor Programmable VBOOT, Power State Operation, SVID
Address Setting, IMAX
• Excellent Dynamic Current Balance Between Phases
• OCP/WOC, OVP, OT Alert, PGOOD
• Small Footprint 40 Ld 5x5 TQFN Package
• Pb-Free (RoHS Compliant)
Applications
•D DR Memory
COMP
200mV/DIV
VDDQ = 1.5V
50mV/DIV
PHASE1/2/3
5V/DIV
26A STEP LOAD
1V/DIV
20µs/DIV
FIGURE 1. FAST TRANSIENT RESPONSE
95
94 1.5V PS1 2ph CCM
1.5V PS0
93
92 1.5V PS2 1ph DE
91
1.35VPS0
90
89 1.35V PS1 2ph CCM
88
1.35VPS2 1ph DE
87
86
85
0 10 20 30 40 50 60 70
LOAD (A)
FIGURE 2. ISL6353EVAL1Z EFFICIENCY vs LOAD
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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ISL6353
Simplified Application Circuit Using Inductor DCR Current Sensing
+5VDUAL VIN
+5VDUAL
RNTC
°C
µP {
VCCSENSE
VSSSENSE
VO1
VO2
VO3
VSUMN
°C
ADDR
PROG2
PROG1
NTC
SDA
ALERT#
SCLK
VW
BOOT1
UG1
PH1
LG1
GND
VIN (5VSB/12V DUAL)
+12V
PH1
COMP
FB
VSEN
RTN
FB2
ISEN1
ISEN2
ISEN3
ISUMN
ISUMP
BOOT2
UG2
PH2
ISL6353
LG2
GND
+5V
PWM3
VCTRL
BOOT
VCC
UGATE
ISL6596 PHASE
PWM
DRIVER GND
LGATE
VSET1
VSET2
PSI
IMON
PH2
+12V
PH3
VO1
VO2
VO3
VDDQ
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Block Diagram
ISL6353
SDA
ALERT#
SCLK
VSET1
VSET2
ADDR
PROG1
PROG2
VR_ON PSI
VREADY
A/D
PROG
T_MONITOR
DIGITAL
INTERFACE
IMON
DAC
D/A
IBAL
IMAX
VBOOT
TMAX
DROOP
# OF PHASES FOR PS1
SET (A/D)
PROG
NTC
VR_HOT#
TEMP MONITOR
T_MONITOR
POWER-ON RESET
(POR)
PHASE CURRENT
BALANCE
DRIVER
VW
RTN
FB2
FB
DAC
+
?
+
+
E/A
-
COMP
DROOP
R3
MODULATOR
DRIVER
DRIVER
ISUMP
ISUMN
IMON
+
-
CURRENT
SENSE
OC AND WOC
PROTECTION
OV PROTECTION
DRIVER
VDD
ISEN1
ISEN2
ISEN3
VIN
BOOT2
UG2
PH2
LG2
GND
PWM3
BOOT1
UG1
PH1
VDDP
LG1
GND
PGOOD
VSEN
OVP
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Pin Configuration
ISL6353
ISL6353
(40 LD TQFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
SDA 1
ALERT# 2
SCLK 3
VR_ON 4
PGOOD 5
IMON 6
VR_HOT# 7
NTC 8
VW 9
COMP 10
GND
(BOTTOM PAD)
30 LG2
29 VDDP
28 PWM3
27 LG1
26 GND
25 PH1
24 UG1
23 BOOT1
22 PROG1
21 VIN
11 12 13 14 15 16 17 18 19 20
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 2, 3 SDA, ALERT#, SCLK Serial communication bus signals connected between the CPU and the voltage regulator.
4
VR_ON
Voltage regulator enable input. A high level logic signal on this pin enables the VR.
5
PGOOD
Open-drain output to indicate the regulator is ready to supply regulated voltage. Use an appropriate external pull-up
resistor.
6
IMON
Output current monitor pin. IMON sources a current proportional to the regulator output current. A resistor
connected from this pin to ground will set a voltage that is proportional to the load current. This voltage is sampled
with an internal ADC to produce a digital IMON signal that can be read through the serial communications bus.
7
VR_HOT#
Thermal overload output indicator.
8 NTC Thermistor input to the VR_HOT# circuit.
9 VW Window voltage set pin used to set the switching frequency. A resistor from this pin to COMP programs the
switching frequency (18kΩ gives approximately 300kHz).
10
COMP
This pin is the output of the error amplifier.
11 FB This pin is the inverting input of the error amplifier.
12 FB2 This pin switches in an RC network from VOUT to FB in PS1 and PS2 modes to help improve transient performance
and phase margin when dropping phases in low power states. There is a switch between the FB2 pin and the FB
pin. The switch is off in the PS0 state and on in the PS1 and PS2 states. If this function is not needed, the pin can
be left open.
13
ISEN3
Individual current sensing input for Phase 3. Leave this pin open when ISL6353 is configured in 2-phase mode.
14
ISEN2
Individual current sensing input for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will disable Phase 2,
and the controller will run in 1-phase mode.
15
ISEN1
Individual current sensing input for Phase 1.
16
VSEN
Output voltage sense pin. Connect to the output voltage (typically VDDQ) at the desired remote voltage sensing
location.
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ISL6353
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
17 RTN Output voltage sense return pin. Connect to the ground at desired remote sensing location.
18, 19
ISUMN and ISUMP Inverting and non-inverting input of the transconductance amplifier for current monitoring and OCP.
20 VDD 5V bias power.
21 VIN Input supply voltage, used for input supply feed-forward compensation.
22
PROG1
The program pin for the voltage regulator IMAX setting. Refer to Table 6.
23
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PH1 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT1 pin.
24 UG1 Output of the Phase 1 high-side MOSFET gate driver. Connect the UG1 pin to the gate of the Phase 1 high-side
MOSFET.
25 PH1 Current return path for the Phase 1 high-side MOSFET gate driver. Connect the PH1 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 1.
26 GND This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
27 LG1 Output of the Phase 1 low-side MOSFET gate driver. Connect the LG1 pin to the gate of the Phase 1 low-side
MOSFET.
28
PWM3
PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase 3 and allow other
phases to operate.
29
VDDP
Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF using an
MLCC capacitor to the ground plane close to the IC.
30 LG2 Output of the Phase 2 low-side MOSFET gate driver. Connect the LG2 pin to the gate of the Phase 2 low-side
MOSFET.
31 GND This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
32 PH2 Current return path for the Phase 2 high-side MOSFET gate driver. Connect the PH2 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2.
33 UG2 Output of the Phase 2 high-side MOSFET gate driver. Connect the UG2 pin to the gate of the Phase 2 high-side
MOSFET.
34
BOOT2
Connect an MLCC capacitor across the BOOT2 and the PH2 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT2 pin.
35
PROG2
The program pin for the voltage regulator VBOOT voltage, droop enable/disable and the number of active phases
for PS1 mode.
36 PSI This pin can be used to set the power state of the controller with external logic signals. By connecting this pin to
ground, the controller will refer only to the power state indicated by the serial communication bus register. If the
pin is connected to a high impedance, the controller will enter the PS1 state. If the pin is connected to a logic high,
the controller will enter the PS2 state.
37
VSET2
This pin is a logic input that can be used in conjunction with VSET1 to program the output voltage of the regulator
with external logic signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to
the VID setting indicated by the serial communication bus register.
38
VSET1
This pin is a logic input that can be used in conjunction with VSET2 to program the output voltage of the regulator
with external signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to the
VID setting indicated by the serial communication bus register.
39 OVP An inverter output, latched high for an overvoltage event. It is reset by POR.
40
ADDR
This pin sets the address offset register, range from 0 to 13 (0h to Dh).
- GND (Bottom Pad) Electrical ground of the IC. Unless otherwise stated, all signals are referenced to the GND pin. Connect this ground
pad to the ground plane through a low impedance path. Recommend use of at least 5 vias to connect to ground
planes in PCB internal layers.
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