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Multiphase PWM Regulator for VR12™ Desktop CPUs
ISL6363
Fully compliant with VR12™ specifications, the ISL6363
provides a complete solution for microprocessor core and
graphics power supplies. It provides two Voltage Regulators
(VRs) with three integrated gate drivers. The first output (VR1)
can be configured as a 4, 3, 2 or 1-phase VR while the second
output (VR2) is a 1-phase VR. The two VRs share a serial control
bus to communicate with the CPU and achieve lower cost and
smaller board areacomparedwith a two-chip approach.
Based on Intersil’s Robust Ripple Regulator R3 Technology™,
the PWM modulator, compared to traditional modulators, has
faster transient settling time, variable switching frequency
during load transients and has improved light load efficiency
with its ability to automatically change switching frequency.
The ISL6363 has several other key features. Both outputs
support DCR current sensing with a single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. Both outputs come with remote voltage sensing,
programmable VBOOT voltage, serial bus address, IMAX, TMAX,
adjustable switching frequency, OC protection and separate
power-good indicators. To reduce output capacitors, the
ISL6363 also has an additional compensation function for
PS1/2 mode and high frequency load transient compensation.
Features
• Serial Data Bus (SVID)
•D ual Outputs:
- Configurable 4, 3, 2 or 1-phase for the 1st Output with 2
Integrated Gate Drivers
- 1-phase for the 2nd Output with Integrated Gate Driver
• Precision Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• PS2 Compensation and High Frequency Load Transient
Compensation
• Differential Remote Voltage Sensing
• Lossless Inductor DCR Current Sensing
•P rogrammable VBOOT Voltage at Start-up
• Resistor Programmable Address, IMAX, TMAX for Both
Outputs
• Adaptive Body Diode Conduction Time Reduction
Applications
•V R12 Desktop Computers
Related Literature
• ISL6363EVAL1Z User Guide
VCORE
50mV/DIV
COMP
1V/DIV
2µs/DIV
65A STEP LOAD
1V/DIV
FIGURE 1. FAST TRANSIENT RESPONSE
1.15
1.10
1.05
1.00
0.95
1.7mLOADLINE
1.1V - PS1
1.1V - PS0
0.90
0 5 101 5 20 253 03 5 40 45 50 55 60 65 70 75 80 85
IOUT (A)
FIGURE 2. ACCURATE LOADLINE, VCORE vs IOUT
September 29, 2011
FN6898.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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ISL6363
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6363CRTZ
ISL6363 CRTZ
0 to +70
48 Ld 6x6 TQFN
L48.6x6
ISL6363IRTZ
ISL6363 IRTZ
-40 to +85
48 Ld 6x6 TQFN
L48.6x6
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6363. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL6363
(48 LD TQFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
SCOMP 1
PGOOD 2
VCC 3
ISUMP 4
Temporary Pinout
Subject to Change
36 PHASEG
35 UGATEG
34 BOOTG
33 LGATEG
ISUMN 5
ISEN1 6
ISEN2 7
GND PAD
(BOTTOM)
32 PVCCG
31 VR_HOT#
30 NTCG
ISEN3 8
29 ISUMNG
ISEN4 9
28 ISUMPG
VSEN 10
27 RTNG
PSICOMP 11
26 FBG
RTN 12
25 COMPG
13 14 15 16 17 18 19 20 21 22 23 24
Pin Descriptions
ISL6363
Bottom
Pad
1
2
3
4, 5
6
7
8
SYMBOL
GND
SCOMP
PGOOD
VCC
ISUMP,
ISUMN
ISEN1
ISEN2
ISEN3
DESCRIPTION
Common ground signal of the IC. Unless otherwise stated, signals are referenced to the GND pin. The pad should also be
used as the thermal pad for heat dissipation.
This pin is a placeholder for potential future functionality. This pin can be left floating.
Power-good open-drain output indicating when VR1 is able to supply a regulated voltage. Pull-up externally with a 680
resistor to +5V or 1kto +3.3V.
+5V bias supply pin. Connect a high quality 0.1µF capacitor from this pin to GND and place it as close to the pin as possible.
A small resistor (2.2for example) between the +5V supply and the decoupling capacitor is recommended.
VR1 current sense input pins for current monitoring, droop current and overcurrent detection.
VR1 phase 1 current sense input pin for phase current balancing.
VR1 phase 2 current sense input pin for phase current balancing.
VR1 phase 3 current sense input pin for phase current balancing.
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ISL6363
Pin Descriptions (Continued)
ISL6363
9
10
11
12
13
14
15
16
17
18
19, 20, 21
22
23
24
25
26
27
28, 29
30
31
32
33
34
35
36
37
38
39
40
SYMBOL
ISEN4
VSEN
PSICOMP
RTN
FB
COMP
VW
NTC
IMON
VR_ON
SDA,
ALERT#,
SCLK
PGOODG
IMONG
VWG
COMPG
FBG
RTNG
ISUMPG,
ISUMNG
NTCG
VR_HOT#
PVCCG
LGATEG
BOOTG
UGATEG
PHASEG
PWM4
PWM3
PHASE2
UGATE2
DESCRIPTION
VR1 phase 4 current sense input pin for phase current balancing.
VR1 remote core voltage sense input.
This pin is used for improving transient response in PS2/3 mode of VR1 by switching in an additional type 3 compensation
network to improve system gain and phase margin. Connect a resistor and capacitor from this pin to the output of VR1 near
the feedback compensation network.
VR1 remote voltage sensing return input. Connect this pin to the remote ground sensing location.
Inverting input of the error amplifier for VR1.
This is a dual function pin. This pin is the output of the error amplifier for VR1. A resistor connected from this pin to GND
programs IMAX for VR1 and VBOOT for both VR1 and VR2. Refer to Table 7 on page 28.
A resistor from this pin to COMP programs the PWM switching frequency for VR1.
One of the thermistor network inputs to the thermal monitoring circuit used to control the VR_HOT# signal. Use this pin to
monitor the temperature of VR1. Place the NTC close to the desired thermal detection point on the PCB.
Current monitoring output pin for VR1. The current sense signal from ISUMN and ISUMP is output on this pin to generate a
voltage proportional to the output current of VR1.
Enable input signal for the controller. A high level logic signal on this pin enables the controller and initiates soft-start for VR1
and VR2.
Data, alert and clock signal for the SVID communication bus between the CPU and VR1 and VR2.
Power-good open-drain output indicating when VR2 is able to supply a regulated voltage. Pull-up externally with a 680
resistor to +5V or 1.0kto 3.3V.
Current monitoring output pin for VR2. The current sense signal from ISUMNG and ISUMPG is output on this pin to generate
a voltage proportional to the output current of VR2.
A resistor from this pin to COMPG programs the PWM switching frequency for VR1.
This is a dual function pin. This pin is the output of the error amplifier for VR2. A resistor connected from this pin to GND
programs IMAX for VR2 and TMAX for both VR1 and VR2. Refer to Table 8 on page 28.
Inverting input of the error amplifier for VR2.
VR2 remote voltage sensing return input. Connect this pin to the remote ground sensing location.
VR2 current sense input pin for current monitoring, droop current and overcurrent detection.
One of the thermistor network inputs to the thermal monitoring circuit used to control the VR_HOT# signal. Use this pin to
monitor the temperature of VR2. Place the NTC close to the desired thermal detection point on the PCB.
Open drain thermal overload output indicator.
Input voltage bias for the internal gate driver for VR2. Connect +12V to this pin. Decouple with at least a 1µF MLCC capacitor
and place it as close to the pin as possible.
Output of the VR2 low-side MOSFET gate driver. Connect this pin to the gate of the VR2 low-side MOSFET.
Connect a MLCC capacitor from this pin to the PHASEG pin. The boot capacitor is charged through an internal boot diode
connected from the PVCCG pin to the BOOTG pin.
Output of the VR2 high-side MOSFET gate drive. Connect this pin to the gate of the VR2 high-side MOSFET.
Current return path for the VR2 high-side MOSFET gate driver. Connect this pin to the node connecting the source of the
high-side MOSFET, the drain of the low-side MOSFET and the output inductor of VR2.
PWM output for phase 4 of VR1. When PWM4 is pulled to +5V VCC, the controller will disable phase 4 of VR1.
PWM output for phase 3 of VR1. When PWM3 is pulled to +5V VCC, the controller will disable phase 3 of VR1.
Current return path for the VR1 phase 2 high-side MOSFET gate driver. Connect this pin to the node connecting the source of
the high-side MOSFET, the drain of the low-side MOSFET and the output inductor of phase 2.
Output of the VR1 phase 2 high-side MOSFET gate drive. Connect this pin to the gate of the high-side MOSFET of phase 2.
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ISL6363
Pin Descriptions (Continued)
ISL6363
41
42
43
44
45
46
47
48
SYMBOL
BOOT2
LGATE2
PVCC
LGATE1
BOOT1
UGATE1
PHASE1
ADDR
DESCRIPTION
Connect an MLCC capacitor from this pin to the PHASE2 pin. The boot capacitor is charged through an internal boot diode
connected from the PVCCG pin to the BOOTG pin.
Output of the VR1 phase 2 low-side MOSFET gate driver. Connect this pin to the gate of the low-side MOSFET of phase 2.
Input voltage bias for the internal gate drivers for VR1. Connect +12V to this pin. Decouplewith at leasta 1µF MLCC capacitor
and place it as close to the pin as possible.
Output of the VR1 phase 1 low-side MOSFET gate driver. Connect this pin to the gate of the low-side MOSFET of phase 1.
Connect an MLCC capacitor from this pin to the PHASE1 pin. The boot capacitor is charged through an internal boot diode
connected from the PVCC pin to the BOOT1 pin.
Output of the VR1 phase 1 high-side MOSFET gate drive. Connect this pin to the gate of the high-side MOSFET of phase 1.
Current return path for the VR1 phase 1 high-side MOSFET gate driver. Connect this pin to the node connecting the source of
the high-side MOSFET, the drain of the low-side MOSFET and the output inductor of phase 1.
A resistor from this pin to GND programs the SVID address for VR1 and VR2. Refer to Table 9 on page 28.
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Block Diagram
ISL6363
VWG
COMPG
RTNG
FBG
ISUMPG
ISUMNG
COMPG
+
+Σ
+
E/A
_
IDROOPG
+
CURRENT
_ SENSE
VR2
MODULATOR
IMONG
NTCG
NTC
VR_HOT#
ADDR
VR_ON
SDA
ALERT#
SCLK
VW
COMP
RTN
FB
PSICOMP
ISUMP
ISUMN
ISEN4
ISEN3
ISEN2
ISEN1
VSEN
TEMP
MONITOR
T_MONITOR
IMAX
VBOOT
TMAX
SET (A/D)
ADDR
DIGITAL
INTERFACE
COMPG
COMP
A/D
D/A
MODE
IMONG
IMON
DAC2
DAC1
MODE2
MODE1
VREADY
COMP
PSICOMP
CIRCUIT
+
_
+
+Σ
+
E/A
_
IDROOP
CURRENT
SENSE
OC FAULT
OV FAULT
VR1
MODULATOR
CURRENT
BALANCING
IMON
GND
OC FAULT
IBAL FAULT
OV FAULT
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
5
BOOTG
UGATEG
PHASEG
LGATEG
PGOODG
VCC
PVCCG
PVCC
SCOMP
PWM4
PWM3
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
PGOOD
FN6898.0
September 29, 2011