FSL176MRT.pdf 데이터시트 (총 16 페이지) - 파일 다운로드 FSL176MRT 데이타시트 다운로드

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August 2012
FSL176MRT
Green-Mode Fairchild Power Switch (FPS™)
Features
Advanced Soft Burst-Mode Operation for
Low Standby Power and Low Audible Noise
Random Frequency Fluctuation for Low EMI
Pulse-by-Pulse Current Limit
Various Protection Functions: Overload Protection
(OLP), Over-Voltage Protection (OVP), Abnormal
Over-Current Protection (AOCP), Internal Thermal
Shutdown (TSD) with Hysteresis, Output-Short
Protection (OSP), and Under-Voltage Lockout (UVLO)
with Hysteresis
Low Operating Current (0.4mA) in Burst Mode
Internal Startup Circuit
Internal High-Voltage SenseFET: 650V
Built-in Soft-Start: 15ms
Auto-Restart Mode
Description
The F SL176MRT is an
integrated Pulse W idth
Modulation (PWM) controller and SenseFET specifically
designed for offline Sw itched-Mode Power Supplies
(SMPS) with minimal external components. T he PW M
controller includes an in
tegrated fixed-frequency
oscillator, Under-Voltage Lockout (UVLO), Leading-
Edge Blanking (LEB), optimized gate driver, internal
soft-start, temperature-co mpensated precise current
sources for loop compensation, and self-protection
circuitry. Compared with a discrete MOSF ET and PW M
controller solution, the F SL176MRT can reduce total
cost, component count, size, and w eight; w hile
simultaneously increasing efficiency , productivity , and
system reliability. T his device provides a basic platform
for cost-effective design of a flyback converter.
Applications
Power Supply for LCD Monitor, STB, and
DVD Combination
Ordering Information
Part Number
Output Power Table(2)
Package
Operating
Junction
Temperature
Current
Limit
RDS(ON)
(Max.)
230VAC ±15%(3)
Adapter(4)
Open
Frame(5)
85~265VAC
Adapter(4)
Open
Frame(5)
Replaces
Device
TO-220
FSL176MRTUDTU
6-Lead(1)
U-
Forming
-40°C ~
+125°C
3.50A 1.6
80W
90W
48W
70W FSGM0765R
Notes:
1. Pb-free package per JEDEC J-STD-020B.
2. The junction temperature can limit the maximum output power.
3. 230V AC or 100/115VAC with voltage doubler.
4. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.
5. Maximum practical continuous power in an open-frame design at 50C ambient temperature.
© 2012 Fairchild Semiconductor Corporation
FSL176MRT • Rev. 1.0.0
www.fairchildsemi.com
http://www.Datasheet4U.com

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Application Circuit
AC
IN
VSTR
Drain
GND
FB VCC
VO
Figure 1. Typical Application Circuit
Internal Block Diagram
VBURST
0.30V / 0.45V
Soft Burst
FB 4
N.C. 5
VCC
Vref
2.0µA
IDELAY
90µA
IFB
Soft-Start
tON<tOSP(1.0μs)
3R
R
VOSP
VSD
7.0V
VCC
VOVP
24.5V
LPF
TSD
VSTR
6
Random
ICH
Vref
VCC Good
OSC
PWM
SQ
RQ
LEB (300ns)
VCC Good
SQ
RQ
Figure 2. Internal Block Diagram
VCC Drain
31
7.5V / 12V
Gate
Driver
VAOCP
2 GND
© 2012 Fairchild Semiconductor Corporation
FSL176MRT • Rev. 1.0.0
2
www.fairchildsemi.com

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Pin Configuration
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
1
2
3
4F
5
6V
Name
Drain
GND
VCC
B
NC
STR
Description
SenseFET Drain. High-voltage power SenseFET drain connection.
Ground. This pin is the control ground and the SenseFET source.
Power Supply . T his pin is the positive supply input, which provides the internal operating
current for both startup and steady-state operation.
Feedback. This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor
should be placed between this pin and GND. If the voltage of this pin reaches 7V, the overload
protection triggers, which shuts down the FPS.
No Connection
Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link.
At startup, the internal high-voltage current source supplies internal bias and charges the
external capacitor connected to the VCC pin. Once VCC reaches 12V, the internal current
source (ICH) is disabled.
© 2012 Fairchild Semiconductor Corporation
FSL176MRT • Rev. 1.0.0
3
www.fairchildsemi.com

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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter
Min.
Max.
Unit
VSTR
VDS
VCC
VFB
IDM
IDS
EAS
PD
TJ
VSTR Pin Voltage
Drain Pin Voltage
VCC Pin Voltage
Feedback Pin Voltage
Drain Current Pulsed
Continuous Switching Drain Current(6)
Single Pulsed Avalanche Energy(7)
Total Power Dissipation (TC=25C)(8)
Maximum Junction Temperature
Operating Junction Temperature(9)
TC=25C
TC=100C
-0.3
6.4
4.0
50
-40
650
650
26
12.0
12.8
390
150
+125
V
V
V
V
A
A
A
mJ
W
C
C
TSTG
ESD
Storage Temperature
Electrostatic
Human Body Model, JESD22-A114
Discharge Capability Charged Device Model, JESD22-C101
-55
+150
4.5
2.0
C
kV
Notes:
6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (DMAX=0.74)
and junction temperature (see Figure 4. ).
7. L=45mH, starting TJ=25C.
8. Infinite cooling condition (refer to the SEMI G30-88).
9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
Figure 4. Repetitive Peak Switching Current
Thermal Impedance
TA=25°C unless otherwise specified.
Symbol Parameter
Value
θJA Junction-to-Ambient Thermal Impedance(10) 63.5
θJC Junction-to-Case Thermal Impedance(11) 2.5
Notes:
10. Free standing without heat sink under natural convection condition, per JEDEC 51-2 and 1-10.
11. Infinite cooling condition per Mil Std. 883C method 1012.1.
Unit
°C/W
°C/W
© 2012 Fairchild Semiconductor Corporation
FSL176MRT • Rev. 1.0.0
4
www.fairchildsemi.com

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Electrical Characteristics
TJ = 25C unless otherwise specified.
Symbol Parameter
SenseFET Section
BVDSS Drain-Source Breakdown Voltage
IDSS Zero-Gate-Voltage Drain Current
RDS(ON) Drain-Source On-State Resistance
CISS Input
Capacitance(12)
COSS Output
Capacitance(12)
tr Rise
Time
tf Fall
Time
td(on) T urn-On Delay
td(off) T urn-Off Delay
Control Section
fS Switching Frequency(12)
fS Switching Frequency Variation(12)
DMAX Maximum Duty Ratio
DMIN
Minimum Duty Ratio
IFB Feedback Source Current
VSTART
VSTOP
UVLO Threshold Voltage
tS/S Internal Soft-Start Time
Burst-Mode Section
VBURH
VBURL Burst-Mode Voltage
VHys
Protection Section
ILIM
VSD
IDELAY
tLEB
VOVP
tOSP
VOSP
tOSP_FB
TSD
THys Hy
Peak Drain Current Limit
Shutdown Feedback Voltage
Shutdown Delay Current
Leading-Edge Blanking Time(12)(14)
Over-Voltage Protection
Output-Short
Protection(12)
Threshold Time
Threshold VFB
VFB Blanking Time
Thermal Shutdown Temperature(12)
Conditions
VCC = 0V, ID = 250A
VDS = 520V, TA = 125C
VGS=10V, ID =1A
VDS = 25V, VGS = 0V, f=1MHz
VDS = 25V, VGS = 0V, f=1MHz
VDS = 325V, ID = 4A, RG=25
VDS = 325V, ID = 4A, RG=25
VDS = 325V, ID = 4A, RG=25
VDS = 325V, ID= 4A, RG=25
VCC = 14V, VFB = 4V
-25C < TJ < 125C
VCC = 14V, VFB = 4V
VCC = 14V, VFB = 0V
VFB=0V
VFB = 0V, VCC Sweep
After Turn-On, VFB = 0V
VSTR = 40V, VCC Sweep
VCC = 14V, VFB Sweep
di/dt = 300mA/s
VCC = 14V, VFB Sweep
VCC = 14V, VFB = 4V
VCC Sweep
OSP Triggered when
tON<tOSP & VFB>VOSP
(Lasts Longer than tOSP_FB)
Shutdown Temperature
steresis
Min. Typ.
650
1.3
674
93
30
26
16
39
61 67
±5
61 67
65 90
11 12
7.0 7.5
15
0.39 0.45
0.26 0.30
150
3.15 3.50
6.45 7.00
1.2 2.0
300
23.0 24.5
0.7 1.0
1.8 2.0
2.0 2.5
130 140
60
Max.
250
1.6
73
±10
73
115
13
8.0
0.51
0.34
3.85
7.55
2.8
26.0
1.3
2.2
3.0
150
Unit
V
A
pF
pF
ns
ns
ns
ns
kHz
%
%
%
A
V
V
ms
V
V
mV
A
V
A
ns
V
s
V
s
C
C
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FSL176MRT • Rev. 1.0.0
5
www.fairchildsemi.com