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8 Mbit SPI Serial Flash
SST25VF080
FEATURES:
SST25VF0808 Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
• Single Voltage Read and Write Operations
– 2.7-3.6V for SST25VF080
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• 33 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC 200 mil body width
PRODUCT DESCRIPTION
SST’s s erial flash family features a four-wire, SPI-com-
patible interface that allows for a low pin-count package
occupying less board space and ultimately lowering total
system costs. SST25VF080 SPI se rial flash memories
are m anufactured wi th S ST’s pr oprietary, h igh pe rfor-
mance CMOS SuperFlash technology. The split-gate cell
design and thick-oxide tunneling injector attain better reli-
ability a nd manufacturability com pared w ith a lternate
approaches.
The SST 25VF080 de vices significantly im prove p erfor-
mance, w hile lo wering p ower con sumption. T he t otal
energy consumed is a fu nction of th e ap plied voltage,
current, and time of application. Since for any given volt-
age range, the SuperFlash technology uses less current
to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less
than a lternative f lash m emory technologies. The
SST25VF080 de vices ope rate with a sing le 2.7-3.6V
power supply.
The SST25VF080 devices are offered in an 8-lead SOIC
package with 200 mil body width. See Figure 1 f or pin
assignments.
©2003 Silicon Storage Technology, Inc.
S71250-00-000
10/03
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
http://www.Datasheet4U.com

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Advance Information
FUNCTIONAL BLOCK DIAGRAM
8 Mbit SPI Serial Flash
SST25VF080
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE# SCK SI SO WP# HOLD#
1250 B1.0
©2003 Silicon Storage Technology, Inc.
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S71250-00-000
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8 Mbit SPI Serial Flash
SST25VF080
PIN DESCRIPTION
Advance Information
CE#
SO
WP#
VSS
18
27
Top View
36
VDD
HOLD#
SCK
4 5 SI
1250 08-soic P1.0
FIGURE 1: PIN ASSIGNMENTS FOR 8-LEAD SOIC
TABLE 1: PIN DESCRIPTION
Symbol Pin Name
SCK Serial Clock
SI Serial Data
Input
SO Serial Data
Output
CE# Chip Enable
WP#
HOLD#
VDD
VSS
Write Protect
Hold
Power Supply
Ground
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the device.
To provide power supply voltage: 2.7-3.6V for SST25VF080
T1.0 1250
©2003 Silicon Storage Technology, Inc.
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Advance Information
PRODUCT IDENTIFICATION
TABLE 2: PRODUCT IDENTIFICATION
Manufacturer’s ID
Device ID
SST25VF080
Address
00000H
00001H
Data
BFH
80H
T2.0 1250
MEMORY ORGANIZATION
The SST25VF080 SuperFlash memory array is organized
in 4 KByte sectors with 32 KByte overlay blocks.
8 Mbit SPI Serial Flash
SST25VF080
DEVICE OPERATION
The S ST25VF080 is accessed through t he SPI ( Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25VF080 supports both Mode 0 (0,0) and Mode 3
(1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 2, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
CE#
MODE 3
SCK MODE 0
MODE 3
MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON'T CARE
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1250 F02.0
FIGURE 2: SPI PROTOCOL
©2003 Silicon Storage Technology, Inc.
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8 Mbit SPI Serial Flash
SST25VF080
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low st ate coincides with the f alling ed ge of th e
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next r eaches the active l ow state.
Similarly, if the rising edge of the HOLD# signal does not
Advance Information
coincide wi th th e S CK a ctive low state, then the d evice
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold m ode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with th e device, H OLD# must be dr iven
active high, and CE# must be driven active low. See Figure
17 for Hold timing.
SCK
HOLD#
Active
Hold
FIGURE 3: HOLD CONDITION WAVEFORM
Active
Hold
Active
1250 F03.0
Write Protection
SST25VF080 pr ovides s oftware W rite pr otection. T he
Write Protect pin (WP#) enables or disables the lock-down
function of the st atus r egister. T he Bl ock-Protection bits
(BP1, BP0, and BPL) in the status register provide Write
protection to thememory array and the status register. See
Table 5 for Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is dr iven lo w, the execution of the Wr ite-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUS-
REGISTER (WRSR) INSTRUCTION
WP#
L1
L0
HX
BPL
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T3.0 1250
©2003 Silicon Storage Technology, Inc.
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