HD61830.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 HD61830 데이타시트 다운로드

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HD61830/HD61830B
LCDC (LCD Timing Controller)
ADE-207-275(Z)
'99.9
Rev. 0.0
Description
The HD61830/HD61830B is a dot matrix liquid crystal graphic display controller LSI that stores the
display data sent from an 8-bit microcontroller in the external RAM to generate dot matrix liquid crystal
driving signals.
It has a graphic mode in which 1-bit data in the external RAM corresponds to the on/off state of 1 dot on
liquid crystal display and a character mode in which characters are displayed by storing character codes in
the external RAM and developing them into the dot patterns with the internal character generator ROM.
Both modes can be provided for various applications.
The HD61830/HD61830B is produced by the CMOS process. Thus, combined with a CMOS
microcontroller it can complete a liquid crystal display device with lower power dissipation.
Features
Dot matrix liquid crystal graphic display controller
Display control capacity
Graphic mode: 512k dots (216 bytes)
Character mode: 4096 characters (212 characters)
Internal character generator ROM: 7360 bits
160 types of 5 × 7 dot characters
32 types of 5 × 11 dot characters
Total 192 characters
Can be extended to 256 characters (4 kbytes max.) with external ROM
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HD61830/HD61830B
Interfaces to 8-bit MPU
Display duty cycle (can be selected by a program)
Static to 1/128 duty cycle
Various instruction functions
Scroll, cursor on/off/blink, character blink, bit manipulation
Display method: Selectable A or B types
Internal oscillator (with external resistor and capacitor) HD61830
Operating frequency
1.1 MHz HD61830
2.4 MHz HD61830B
Low power dissipation
Power supply: Single +5 V ±10%
CMOS process
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Differences between Products
HD61830 and HD61830B
Oscillator
Operating frequency
Pin arrangement
and signal name
Package marking
to see figure
HD61830
Internal or external
1.1 MHz
Pin 6: C
Pin 7: R
Pin 9: CPO
A
HD61830/HD61830B
HD61830B
External only
2.4 MHz
Pin 6: CE
Pin 7: OE
Pin 9: NC
B
Package Marking
3D13
Lot No.
A HD61830A00
JAPAN
3D13
Lot No.
B HD61830B00
JAPAN
Ordering Information
Type No.
HD61830A00H
HD61830B00H
Package
60-pin plastic QFP (FP-60)
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HD61830/HD61830B
Pin Arrangement
(CE) C
(OE) R
CR
(NC) CPO
FLM
CL1
SYNC
WE
RES
CS
E
R/W
RS
MA
GND
DB7
DB6
DB5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
FP-60
(Top view)
54 MA10
53 MA11
52 MA12
51 MA13
50 MA14
49 MA15
48 D2
47 D1
46 CL2
45 RD0
44 RD1
43 RD2
42 RD3
41 RD4
40 RD5
39 RD6
38 RD7
37 MD0
36 MD1
( ) is for HD61830B
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HD61830/HD61830B
Terminal Functions
Symbol
DB0–DB7
CS
R/W
RS
E
CR
C
R
CPO
CE
OE
NC
MA0–MA15
MD0–MD7
RD0–RD7
WE
CL2
CL1
FLM
MA
MB
D1
D2
Pin Number
28–21
15
17
18
16
8
6
7
9
6
7
9
4–1, 60–49
37–30
45–38
13
46
11
10
19
5
47
48
I/O Function
I/O Data bus: Three-state I/O common terminal
Data is transferred to MPU through DB0 to DB7.
I Chip select: Selected state with CS = 0
I Read/Write:R/W = 1: MPU HD61830
R/W = 0: MPU HD61830
I Register select: RS = 1: Instruction register
RS = 0: Data register
I Enable: Data is written at the fall of E
Data can be read while E is 1
I CR oscillator (HD61830), External clock input (HD61830B)
— CR oscillator to capacitor (HD61830 only)
— CR oscillator to resistor (HD61830 only)
O Clock signal for HD61830 in slave mode (HD61830 only)
O Chip enable (HD61830B only)
CE = 0: Chip enables make external RAM in active
O Output enable (HD61830B only)
OE = 1: Output enable informs external RAM that HD61830B requires
data bus
Open Unused terminal. Don’t connect any wires to this terminal
(HD61830B only)
O External RAM address output
In character mode, the line code for external CG is output through
MA12 to MA15 (0: Character 1st line, F: Character 16th line)
I/O Display data bus: Three-state I/O common terminal
I ROM data input: Dot data from external character generator is input
O Write enable: Write signal for external RAM
O Display data shift clock for LCD drivers
O Display data latch signal for LCD drivers
O Frame signal for display synchronization
O Signal for converting liquid crystal driving signal into AC, A type
O Signal for converting liquid crystal driving signal into AC, B type
O Display data serial output
D1: For upper half of screen
D2: For lower half of screen
SYNC
12
RES
14
I/O Synchronous signal for parallel operation
Three-state I/O common terminal (with pull-up MOS)
Master: Synchronous signal is output
Slave: Synchronous signal is input
I Reset: Reset = 0 results in display off, slave mode and Hp = 6
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