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®
Data Sheet
VR11.1 Compatible Synchronous
Rectified Buck MOSFET Drivers
The ISL6622 is a high frequency MOSFET driver designed to
drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. The advanced
PWM protocol of ISL6622 is specifically designed to work
with Intersil VR11.1 controllers and combined with
N-Channel MOSFETs, form a complete core-voltage regulator
solution for advanced microprocessors. When ISL6622
detects a PSI protocol sent by an Intersil VR11.1 controller, it
activates Diode Emulation (DE) and Gate Voltage
Optimization Technology (GVOT) operation; otherwise, it
operates in normal Continuous Conduction Mode (CCM)
PWM mode.
In the 8 Ld SOIC package, the ISL6622 drives the upper and
lower gates to VCC during normal PWM mode, while the
lower gate drops down to a fixed 5.75V (typically) during PSI
mode. The 10 Ld DFN part offers more flexibility: the upper
gate can be driven from 5V to 12V via the UVCC pin, while the
lower gate has a resistor-selectable drive voltage of 5.75V,
6.75V, and 7.75V (typically) during PSI mode. This provides
the flexibility necessary to optimize applications involving
trade-offs between gate charge and conduction losses.
To further enhance light load efficiency, the ISL6622 enables
diode emulation operation during PSI mode. This allows
Discontinuous Conduction Mode (DCM) by detecting when
the inductor current reaches zero and subsequently turning
off the low side MOSFET to prevent it from sinking current.
An advanced adaptive shoot-through protection is integrated
to prevent both the upper and lower MOSFETs from
conducting simultaneously and to minimize dead time. The
ISL6622 has a 20kΩ integrated high-side gate-to-source
resistor to prevent self turn-on due to high input bus dV/dt.
This driver also has an overvoltage protection feature
operational while VCC is below the POR threshold: the
PHASE node is connected to the gate of the low side
MOSFET (LGATE) via a 10kΩ resistor, limiting the output
voltage of the converter close to the gate threshold of the low
side MOSFET, dependent on the current being shunted,
which provides some protection to the load should the upper
MOSFET(s) become shorted.
ISL6622
October 30, 2008
FN6470.2
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-through Protection
• Integrated LDO for Selectable Lower Gate Drive Voltage
(5.75V, 6.75V, 7.75V) to Optimize Light Load Efficiency
• 36V Internal Bootstrap Diode
• Advanced PWM Protocol (Patent Pending) to Support PSI
Mode, Diode Emulation, Three-State Operation
• Diode Emulation for Enhanced Light Load Efficiency
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Integrated High-Side Gate-to-Source Resistor to Prevent
from Self Turn-On due to High Input Bus dV/dt
• Pre-POR Overvoltage Protection for Start-up and
Shutdown
• Power Rails Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Applications
• High Light Load Efficiency Voltage Regulators
• Core Regulators for Advanced Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck
Regulators” for Power Train Design, Layout Guidelines,
and Feedback Compensation Design
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6622
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6622CBZ*
6622 CBZ
0 to +70
8 Ld SOIC
M8.15
ISL6622CRZ*
622Z
0 to +70
10 Ld 3x3 DFN
L10.3x3
ISL6622IBZ*
6622IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL6622IRZ*
622I
-40 to +85
10 Ld 3x3 DFN
L10.3x3
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020..
Pinouts
ISL6622
(8 LD SOIC)
TOP VIEW
ISL6622
(10 LD 3x3 DFN)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 VCC
6 LVCC
5 LGATE
UGATE 1
BOOT 2
GD_SEL 3
PWM 4
GND 5
GND
10 PHASE
9 VCC
8 UVCC
7 LVCC
6 LGATE
Block Diagrams
UVCC
GD_SEL
ISL6622
LDO
VCC
PWM
+5V LVCC
11.2k
9.6k
POR/
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
BOOT
UGATE
20k
PHASE
10k
LVCC
LGATE
GND
UVCC = VCC FOR SOIC
LVCC = 5.75V (TYPICALLY) @ 50mA FOR SOIC
2 FN6470.2
October 30, 2008

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Typical Application Circuit
+5V
VTT
VR_RDY
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI
VR_FAN
VR_HOT
VIN
FB COMP VCC DAC
REF
VDIFF
VSEN
RGND
EN_VTT
PWM1
ISEN1-
ISEN1+
ISL6334
PWM2
ISEN2-
ISEN2+
PWM3
ISEN3-
ISEN3+
EN_PWR
GND
IMON
TCOMP
PWM4
ISEN4-
ISEN4+
TM OFS FS SS
+5V +5V
NTC
ISL6622
+12V
LVCC
BOOT
VCC
PWM
ISL6622
DRIVER
UGATE
PHASE
LGATE
GND
+12V
PVCC
BOOT
VCC
PWM
ISL6612
DRIVER
UGATE
PHASE
LGATE
GND
+12V
PVCC
BOOT
VCC
PWM
ISL6612
DRIVER
UGATE
PHASE
LGATE
GND
+12V
PVCC
BOOT
VCC
PWM
ISL6612
DRIVER
UGATE
PHASE
LGATE
GND
VIN
VIN
VIN
VIN
3
µP
LOAD
FN6470.2
October 30, 2008

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ISL6622
Absolute Maximum Ratings
Supply Voltage (VCC, UVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3VDC to VLVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VLVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<200ns, 10µJ) to 30V (<200ns, VBOOT-GND<36V)
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 100
N/A
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range
ISL6622IBZ, ISL6622IRZ . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
ISL6622CBZ, ISL6622CRZ . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
UVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 13.2V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
4. Limits should be considered typical and are not production tested.
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT (Note 4)
No Load Switching Supply Current
Standby Supply Current
IVCC
ISL6622CBZ and ISL6622IBZ,
fPWM = 300kHz, VVCC = 12V
- 8.2 - mA
IVCC
IUVCC
ISL6622CRZ and ISL6622IRZ,
fPWM = 300kHz, VVCC = 12V
- 6.2 - mA
- 2.0 - mA
IVCC
ISL6622CBZ and ISL6622IBZ, PWM
-
5.7
-
mA
Transition from 0V to 2.5V
POWER-ON RESET
IVCC
ISL6622CRZ and ISL6622IRZ, PWM
-
5
- mA
IUVCC
Transition from 0V to 2.5V
- 0.7 - mA
VCC Rising Threshold
6.25 6.45 6.70
V
VCC Falling Threshold
4.8 5.0 5.25 V
LVCC Rising Threshold (Note 4)
- 4.4 -
V
LVCC Falling Threshold (Note 4)
- 3.4 -
V
PWM INPUT (See “TIMING DIAGRAM” on page 6)
Input Current (Note 4)
PWM Rising Threshold (Note 4)
IPWM
VPWM = 5V
VPWM = 0V
VCC = 12V
- 500 -
- -430 -
- 3.4 -
µA
µA
V
PWM Falling Threshold (Note 4)
VCC = 12V
- 1.6 -
V
Three-State Lower Gate Falling Threshold (Note 4)
VCC = 12V
- 1.6 -
V
Three-State Lower Gate Rising Threshold (Note 4)
VCC = 12V
- 1.1 -
V
Three-State Upper Gate Rising Threshold (Note 4)
VCC = 12V
- 3.2 -
V
4 FN6470.2
October 30, 2008

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ISL6622
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Three-State Upper Gate Falling Threshold (Note 4)
VCC = 12V
- 2.8 -
V
UGATE Rise Time (Note 4)
tRU VVCC = 12V, 3nF Load, 10% to 90% - 26 -
LGATE Rise Time (Note 4)
tRL VVCC = 12V, 3nF Load, 10% to 90% - 18 -
UGATE Fall Time (Note 4)
tFU VVCC = 12V, 3nF Load, 90% to 10% - 18 -
LGATE Fall Time (Note 4)
tFL
VVCC = 12V, 3nF Load, 90% to 10%
-
12
-
UGATE Turn-On Propagation Delay (Note 4)
tPDHU VVCC = 12V, 3nF Load, Adaptive
- 20 -
LGATE Turn-On Propagation Delay (Note 4)
tPDHL VVCC = 12V, 3nF Load, Adaptive
- 10 -
UGATE Turn-Off Propagation Delay (Note 4)
tPDLU VVCC = 12V, 3nF Load
- 10 -
LGATE Turn-Off Propagation Delay (Note 4)
tPDLL
VVCC = 12V, 3nF Load
- 10 -
Diode Braking Holdoff Time (Note 4)
tUG_OFF_DB VVCC = 12V
- 60 -
Minimum LGATE ON-Time At Diode Emulation
tLG_ON_DM VVCC = 12V
230 330 450
OUTPUT (Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
IU_SOURCE VVCC = 12V, 3nF Load
RU_SOURCE 20mA Source Current
IU_SINK VVCC = 12V, 3nF Load
RU_SINK 20mA Sink Current
IL_SOURCE VVCC = 12V, 3nF Load
RL_SOURCE 20mA Source Current
IL_SINK VVCC = 12V, 3nF Load
RL_SINK 20mA Sink Current
- 1.25 -
- 2.0 -
- 2-
- 1.35 -
- 2-
- 1.35 -
- 3-
- 0.90 -
A
Ω
A
Ω
A
Ω
A
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
- 3 GD_SEL This pin sets the LG drive voltage in PSI mode.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see the three-state PWM Input section on page 6 for further details. Connect this pin to the PWM output of the
controller.
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 LVCC This pin provides power for the LGATE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
- 8 UVCC This pin provides power to the upper gate drive. Its operating range is +5V to 12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
7 9 VCC Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC and to the LDO for the
lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
- 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5 FN6470.2
October 30, 2008