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CAT28C512/513
512K-Bit CMOS PARALLEL EEPROM
FEATURES
s Fast Read Access Times: 120/150 ns
s Low Power CMOS Dissipation:
–Active: 50 mA Max.
–Standby: 200 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–5ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel EEPROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
BLOCK DIAGRAM
s Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC and TSOP packages.
A7A15
VCC
CE
OE
WE
A0A6
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
65,536 x 8
EEPROM
ARRAY
128 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0I/O7
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1007, Rev. I

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CAT28C512/513
PIN CONFIGURATION
DIP Package (L)
PLCC Package (N, G)
PLCC Package (N, G)
NC 1
32 VCC
NC 2
31 WE
A15 3
A12 4
A7 5
30 NC
29 A14
28 A13
4 3 2 1 32 31 30
A7 5
29 A14
A6 6
28 A13
A5 7
27 A8
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A6
A5
A4
A3
A2
A1
A0
6 27
7 26
8 25
9 24
10 23
11 22
12 21
A8
A9
A11
OE
A10
CE
I/O7
A4
A3
A2
A1
A0
I/O0
8 CAT28C512 26
9 TOP VIEW 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A9
A11
OE
A10
CE
I/O7
A3
A2
A1
A0
NC
I/O0
8
CAT28C513
26
9 TOP VIEW 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
NC
OE
A10
CE
I/O7
I/O6
I/O0 13 20 I/O6
I/O1 14 19 I/O5
I/O2 15 18 I/O4
VSS 16 17 I/O3
TSOP Package (8mmx20mm) (T, H)
A11
A9
A8
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CAT28C512
TOP VIEW
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 Vss
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
PIN FUNCTIONS
Pin Name
A0A15
Function
Address Inputs
Pin Name
WE
I/O0I/O7
CE
OE
Data Inputs/Outputs
Chip Enable
Output Enable
VCC
VSS
NC
Function
Write Enable
5V Supply
Ground
No Connect
Doc. No. MD-1007, Rev. I
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice

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CAT28C512/513
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55°C to +125°C
Storage Temperature ....................... 65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... 2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
*COMMENT
Stresses above those listed under Absolute Maximum
Ratingsmay cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min
100,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol
ICC
Parameter
VCC Current (Operating, TTL)
Min Typ
Max.
50
Units
mA
Test Conditions
CE = OE = VIL, f=6MHz
All I/Os Open
ICCC(5)
VCC Current (Operating, CMOS)
25 mA CE = OE = VILC, f=6MHz
All I/Os Open
ISB
ISBC(6)
VCC Current (Standby, TTL)
VCC Current (Standby, CMOS)
3 mA CE = VIH, All I/Os Open
200 µA CE = VIHC,
All I/Os Open
ILI Input Leakage Current
-10
10 µA VIN = GND to VCC
ILO Output Leakage Current
-10
10 µA VOUT = GND to VCC,
CE = VIH
VIH(6)
High Level Input Voltage
2
VCC +0.3 V
VIL(5)
Low Level Input Voltage
-1
0.8 V
VOH High Level Output Voltage
2.4
V IOH = 400µA
VOL Low Level Output Voltage
0.4 V IOL = 2.1mA
VWI Write Inhibit Voltage
3.5
V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC +1V.
(5) VILC = 0.3V to +0.3V.
(6) VIHC = VCC 0.3V to VCC +0.3V.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1007, Rev . I

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CAT28C512/513
MODE SELECTION
Mode
CE WE OE I/O Power
Read
L
H
L
DOUT
ACTIVE
Byte Write (WE Controlled)
L
H DIN ACTIVE
Byte Write (CE Controlled)
L H DIN ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
CI/O(1)
Input/Output Capacitance
CIN(1)
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
A.C. CHARACTERISTICS, Read Cycle
VCC=5V + 10%, Unless otherwise specified
28C512/513-12 28C512/513-15
Symbol Parameter
Min. Max. Min. Max. Units
tRC Read Cycle Time
tCE CE Access Time
120
120
150
150
ns
ns
tAA Address Access Time
120
tOE OE Access Time
50
tLZ(1)
CE Low to Active Output
0
tOLZ(1) OE Low to Active Output
0
tHZ(1)(2) CE High to High-Z Output
50
tOHZ(1)(2) OE High to High-Z Output
50
tOH(1)
Output Hold from Address Change 0
150 ns
70 ns
0 ns
0 ns
50 ns
50 ns
0 ns
Power-Up Timing
Symbol
tPUR (1)
tPUW (2)
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min.
5
Max
100
10
Units
µs
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. MD-1007, Rev. I
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice

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A.C. CHARACTERISTICS, Write Cycle
VCC=5V+10%, unless otherwise specified
Symbol Parameter
28C512/513-12 28C512/513-15
Min. Max. Min. Max. Units
tWC Write Cycle Time
5 5 ms
tAS Address Setup Time
0 0 ns
tAH
tCS
tCH
tCW(3)
tOES
tOEH
tWP(3)
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
50 50
00
00
100 100
00
00
100 100
ns
ns
ns
ns
ns
ns
ns
tDS Data Setup Time
50 50 ns
tDH Data Hold Time
tINIT(1) Write Inhibit Period After Power-up
tBLC(1)(4) Byte Load Cycle Time
0
5
0.1
0
10 5 10
100 0.1 100
ns
ms
µs
CAT28C512/513
Figure 1. A.C. Testing Input/Output Waveform(2)
VCC - 0.3V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
DEVICE
UNDER
TEST
1.3V
1N914
3.3K
OUT
CL = 100 pF
Note:
CL INCLUDES JIG CAPACITANCE
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-1007, Rev . I