MN103L26.pdf 데이터시트 (총 13 페이지) - 파일 다운로드 MN103L26 데이타시트 다운로드

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MN103L09/10/11/12/13/14/15/16/17/18/19/20/
21/22/23/24/25/26/27 Series
32-bit Single-chip Microcontroller
Overview
The MN103LF series of 32-bit single-chip microcomputers have multiple types of peripheral functions. This LSI series is well suited for
camera, TV, VCR, AV, printer, telephone, FAX machine, air-conditioner, music instrument and other applications.
This LSI series has flexible and optimized hardware configurations and simple efficient instruction set. This LSI series incorporates an
internal ROM of 1048 KB (maximum) and RAM of 76 KB (maximum), 11 external interrupts, 96 internal interrupts including non-maskable
interrupt, 26 timer counters, 14 sets of serial interfaces, A/D converter, D/A converter, 2 sets of watchdog timer, DMA, CAN, and IEBus
interface.
In addition, this LSI series has 5 oscillation circuits (external high frequency: 4 MHz to 20 MHz/ external low frequency:32.768 kHz/ internal
high frequency: 20 MHz/ internal low frequency: 30 kHz/ PLL: frequency multiplier of high or low frequency).
The internal clock can be switched to four oscillation clock except the internal low oscillation. The internal clock is generated by dividing the
oscillation clock or PLL clock. The best operation clock for the system can be selected by switching its frequency ratio by programming.
A machine cycle (minimum instruction execution time) is 25 ns (internal operating condition: 1.8 V, 40 MHz).
Product Summary
This datasheet describes the following model.
Series
Model
Pin Number ROM Size RAM Size *1
MN103L09
MN103LF09R
MN103LF09Q
144
1048 KB
792 KB
76 KB
MN103LF13R
MN103LF13Q
1048 KB
792 KB
76 KB
MN103L10/
MN103L13
MN103LF10R
MN103LF10Q
MN103LF10N
100
1048 KB
792 KB
64 KB
536 KB
40 KB
MN103LF10M
408 KB
32 KB
MN103LF10K
280 KB
20 KB
MN103LF14R
MN103LF14Q
1048 KB
792 KB
76 KB
MN103L11/
MN103L14
MN103LF11R
MN103LF11Q
MN103LF11N
128
1048 KB
792 KB
64 KB
536 KB
40 KB
MN103LF11M
408 KB
32 KB
MN103LF11K
280 KB
20 KB
MN103L12/
MN103L15
MN103LF15R
MN103LF15Q
MN103LF12R
MN103LF12Q
1048 KB
792 KB
76 KB
144
1048 KB
792 KB
64 KB
MN103LF12N
536 KB
40 KB
MN103LF19R
MN103LF19Q
1048 KB
792 KB
76 KB
MN103L16/
MN103L19
MN103LF16R
MN103LF16Q
MN103LF16N
100
1048 KB
792 KB
64 KB
536 KB
40 KB
MN103LF16M
408 KB
32 KB
MN103LF16K
280 KB
20 KB
Note) *1: When using On-Chip Debug function, the debugger take over 500 Byte in size
In-vehicle LAN
CAN/IEBus
IEBus
Publication date: February 2014
Ver. BEM
Package
LQFP144-P-2020D
LQFP100-P-1414C
LQFP128-P-1818F
LQFP144-P-2020D
LQFP100-P-1414C
1

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MN103L09/10/11/12/13/14/15/16/17/18/19/20/21/22/23/24/25/26/27 Series
Product Summary (continued)
This datasheet describes the following model.
Series
Model
Pin Number ROM Size RAM Size *1
MN103LF20R
MN103LF20Q
1048 KB
792 KB
76 KB
MN103L17/
MN103L20
MN103LF17R
MN103LF17Q
MN103LF17N
128
1048 KB
792 KB
64 KB
536 KB
40 KB
MN103LF17M
408 KB
32 KB
MN103LF17K
280 KB
20 KB
MN103L18/
MN103L21
MN103LF21R
MN103LF21Q
MN103LF18R
MN103LF18Q
1048 KB
792 KB
76 KB
144
1048 KB
792 KB
64 KB
MN103LF18N
536 KB
40 KB
MN103LF25R
MN103LF25Q
1048 KB
792 KB
76 KB
MN103L22/
MN103L25
MN103LF22R
MN103LF22Q
MN103LF22N
100
1048 KB
792 KB
64 KB
536 KB
40 KB
MN103LF22M
408 KB
32 KB
MN103LF22K
280 KB
20 KB
MN103LF26R
MN103LF26Q
1048 KB
792 KB
76 KB
MN103L23/
MN103L26
MN103LF23R
MN103LF23Q
MN103LF23N
128
1048 KB
792 KB
64 KB
536 KB
40 KB
MN103LF23M
408 KB
32 KB
MN103LF23K
280 KB
20 KB
MN103L24/
MN103L27
MN103LF27R
MN103LF27Q
MN103LF24R
MN103LF24Q
1048 KB
792 KB
76 KB
144
1048 KB
792 KB
64 KB
MN103LF24N
536 KB
40 KB
Note) *1: When using On-Chip Debug function, the debugger take over 500 Byte in size
In-vehicle LAN
CAN
Package
LQFP128-P-1818F
LQFP144-P-2020D
LQFP100-P-1414C
LQFP128-P-1818F
LQFP144-P-2020D
Ver. BEM
2

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MN103L09/10/11/12/13/14/15/16/17/18/19/20/21/22/23/24/25/26/27 Series
Features
CPU core
MN103L core (The instruction set is compatible MN103S series)
Memory space 4 GB (instruct/data common use)
LOAD-STORE architecture (3-stage pipeline)
Machine cycle
High-speed mode 25 ns/ 40 MHz (Max)
Low-speed mode 30.3 ms/ 33 kHz (Max)
Operation mode
NORMAL mode
SLOW mode
HALT mode
STOP mode
(CPU clock operation, Peripheral circuit clock operation mode)
(CPU clock operation, Peripheral circuit clock operation mode)
(CPU clock stop, Peripheral circuit clock operation mode)
(All clocks stop mode)
Clock oscillation circuit : 5 circuits
External high-speed oscillation (clkosc)
External low-speed oscillation (clkx)
Internal high-speed oscillation (clkrc)
Internal low-speed oscillation (clkrcx)
PLL output (clkpll)
: Crystal oscillator/ Ceramic oscillator
: 4 MHz to 20 MHz
: Crystal oscillator/ Ceramic oscillator
: 32.768 kHz
: 20 MHz
: 30 kHz
: 60 MHz to 120 MHz
Clock multiple circuit (PLL)
Multiplication rate
: 4, 6, 8, 10, 12, 16, 20 multiplied clock of clkoscsel
2440 to 3660 multiplied clock of clkx
Clock dividing
: 2, 3 divided of clkpll
PLL output dividing clock: 20 MHz to 40 MHz (clkplldiv)
Internal operation clock: 6 types
CPU clock (clkcpu)
Frequency
: 40 MHz (Max)
Clock source
: clkplldiv, clkosc, clkrc, clkx
Clock dividing
: 1, 2, 4, 8, 16, 32, 64 divided of clock source
Peripheral bus clock (clkbus)
Frequency
: 20 MHz (Max)
Clock source
: clkplldiv, clkosc, clkrc, clkx
Clock dividing
: 2, 4, 8, 16, 32, 64, 128 divided of clock source
(This setting is independent from the dividing clock setting of clkcpu. Set the frequency of clkbus to
less than clkcpu.)
Peripheral high-speed clock (clksp)
Frequency
: 22 MHz (Max)
Clock source
: clkrc, clkosc, clkplldiv
Clock dividing
: 1, 2, 4, 8, 16 divided of clock source
High-speed oscillation clock (clkoscsel)
Frequency
: 22 MHz (Max)
Clock source
: clkrc, clkosc
Internal low-speed oscillation clock (clkrcx)
Frequency
: 33 kHz (Max)
Low-speed oscillation clock (clksx)
Frequency
: 33 kHz (Max)
Clock source
: clkrcx, clkxsel
Ver. BEM
3