MT29C8G96MAZAPDJV-6IT.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 MT29C8G96MAZAPDJV-6IT 데이타시트 다운로드

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Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
NAND Flash and Mobile LPDDR
168-Ball Package-on-Package (PoP) MCP
Combination Memory (TI OMAP)
MT29C4G48MAYAPAKQ-5 IT, MT29C4G48MAZAPAKQ-5 IT,
MT29C4G48MAZAPAKQ-6 IT, MT29C4G96MAZAPCJG-5 IT,
MT29C4G96MAZAPCJG-6 IT, MT29C8G96MAZAPDJV-5 IT,
MT29C8G96MAZAPDJV-6 IT
Features
Micron® NAND Flash and LPDDR components
RoHS-compliant, “green” package
Separate NAND Flash and LPDDR interfaces
Space-saving multichip package/package-on-package
combination
Low-voltage operation (1.70–1.95V)
Industrial temperature range: –40°C to +85°C
NAND Flash-Specific Features
Organization
Page size
x8: 2112 bytes (2048 + 64 bytes)
x16: 1056 words (1024 + 32 words)
Block size: 64 pages (128K + 4K bytes)
Mobile LPDDR-Specific Features
No external voltage reference required
No minimum clock rate requirement
1.8V LVCMOS-compatible inputs
Programmable burst lengths
Partial-array self refresh (PASR)
Deep power-down (DPD) mode
Selectable output drive strength
STATUS REGISTER READ (SRR) supported1
Notes: 1. Contact factory for remapped SRR output.
2. For physical part markings, see Part Number-
ing Information (page 2).
Figure 1: PoP Block Diagram
NAND Flash
Power
NAND Flash
Device
LPDRAM Power
LPDRAM
Device
NAND Flash
Interface
LPDRAM
Interface
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. F 03/10
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.

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Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
Part Numbering Information
Micron NAND Flash and LPDRAM devices are available in different configurations and densities. The MCP/PoP
part numbering guide is available at www.micron.com/numbering.
Figure 2: Part Number Chart
MT 29C XX XXX X X X X X X X XX
Micron Technology
Product Family
NAND Flash Density
LPDRAM Density
Operating Voltage Range
NAND Flash Configuration
Production Status
Operating Temperature Range
LPDRAM Access Time
Package Codes
Chip Count
LPDRAM Configuration
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,
an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are
cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder.
To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/
Label,” at www.micron.com/csn.
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. F 03/10
2 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

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Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Contents
MCP General Description ............................................................................................................................... 11
Ball Assignments and Descriptions ................................................................................................................. 12
Electrical Specifications .................................................................................................................................. 16
Device Diagrams ............................................................................................................................................ 17
Package Dimensions ...................................................................................................................................... 19
4Gb, 8Gb: x8, x16 NAND Flash Memory ........................................................................................................... 22
Features ..................................................................................................................................................... 22
General Description ................................................................................................................................... 23
Architecture ................................................................................................................................................... 24
Device and Array Organization ....................................................................................................................... 25
Asynchronous Interface Bus Operation ........................................................................................................... 29
Asynchronous Enable/Standby ................................................................................................................... 29
Asynchronous Commands .......................................................................................................................... 29
Asynchronous Addresses ............................................................................................................................ 31
Asynchronous Data Input ........................................................................................................................... 32
Asynchronous Data Output ........................................................................................................................ 33
Write Protect .............................................................................................................................................. 34
Ready/Busy# .............................................................................................................................................. 34
Device Initialization ....................................................................................................................................... 39
Command Definitions .................................................................................................................................... 40
Reset Operations ............................................................................................................................................ 43
RESET (FFh) ............................................................................................................................................... 43
Identification Operations ................................................................................................................................ 44
READ ID (90h) ............................................................................................................................................ 44
READ ID Parameter Tables ............................................................................................................................. 45
READ PARAMETER PAGE (ECh) ...................................................................................................................... 47
Bare Die Parameter Page Data Structure Tables .............................................................................................. 48
READ UNIQUE ID (EDh) ................................................................................................................................ 51
Feature Operations ......................................................................................................................................... 52
SET FEATURES (EFh) ................................................................................................................................. 53
GET FEATURES (EEh) ................................................................................................................................. 54
Status Operations ........................................................................................................................................... 57
READ STATUS (70h) ................................................................................................................................... 58
READ STATUS ENHANCED (78h) ............................................................................................................... 58
Column Address Operations ........................................................................................................................... 60
RANDOM DATA READ (05h-E0h) ................................................................................................................ 60
RANDOM DATA READ TWO-PLANE (06h-E0h) ........................................................................................... 61
RANDOM DATA INPUT (85h) ..................................................................................................................... 62
PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 63
Read Operations ............................................................................................................................................. 65
READ MODE (00h) ..................................................................................................................................... 67
READ PAGE (00h-30h) ................................................................................................................................ 67
READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 68
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 69
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 71
READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... 72
Program Operations ....................................................................................................................................... 74
PROGRAM PAGE (80h-10h) ........................................................................................................................ 75
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 75
Erase Operations ............................................................................................................................................ 77
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. F 03/10
3 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

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Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
ERASE BLOCK (60h-D0h) ............................................................................................................................ 77
ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 78
Internal Data Move Operations ....................................................................................................................... 79
READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................ 80
PROGRAM FOR INTERNAL DATA MOVE (85h–10h) .................................................................................... 83
PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................ 84
Block Lock Feature ......................................................................................................................................... 85
WP# and Block Lock ................................................................................................................................... 85
UNLOCK (23h-24h) .................................................................................................................................... 85
LOCK (2Ah) ................................................................................................................................................ 88
LOCK TIGHT (2Ch) ..................................................................................................................................... 89
BLOCK LOCK READ STATUS (7Ah) ............................................................................................................. 90
One-Time Programmable (OTP) Operations .................................................................................................... 92
Legacy OTP Commands .............................................................................................................................. 92
OTP DATA PROGRAM (80h-10h) ................................................................................................................. 93
RANDOM DATA INPUT (85h) .................................................................................................................... 94
OTP DATA PROTECT (80h-10) .................................................................................................................... 95
OTP DATA READ (00h-30h) ........................................................................................................................ 97
Two-Plane Operations .................................................................................................................................... 99
Two-Plane Addressing ................................................................................................................................ 99
Interleaved Die (Multi-LUN) Operations ........................................................................................................ 108
Error Management ........................................................................................................................................ 109
Internal ECC and Spare Area Mapping for ECC ............................................................................................... 111
Electrical Specifications ................................................................................................................................. 113
Electrical Specifications – DC Characteristics and Operating Conditions ......................................................... 115
Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 117
Electrical Specifications – Program/Erase Characteristics ................................................................................ 120
Asynchronous Interface Timing Diagrams ...................................................................................................... 121
2Gb: x16, x32 Mobile LPDDR SDRAM ............................................................................................................. 133
Features .................................................................................................................................................... 133
General Description .................................................................................................................................. 134
Functional Block Diagrams ............................................................................................................................ 135
Electrical Specifications ................................................................................................................................. 137
Electrical Specifications – IDD Parameters ....................................................................................................... 140
Electrical Specifications – AC Operating Conditions ........................................................................................ 146
Output Drive Characteristics .......................................................................................................................... 151
Functional Description .................................................................................................................................. 154
Commands ................................................................................................................................................... 155
DESELECT ............................................................................................................................................... 156
NO OPERATION ....................................................................................................................................... 156
LOAD MODE REGISTER ........................................................................................................................... 156
ACTIVE .................................................................................................................................................... 156
READ ....................................................................................................................................................... 157
WRITE ..................................................................................................................................................... 158
PRECHARGE ............................................................................................................................................ 159
BURST TERMINATE ................................................................................................................................. 160
AUTO REFRESH ....................................................................................................................................... 160
SELF REFRESH .......................................................................................................................................... 161
DEEP POWER-DOWN ............................................................................................................................... 161
Truth Tables .................................................................................................................................................. 162
State Diagram ............................................................................................................................................... 167
Initialization ................................................................................................................................................. 168
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. F 03/10
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

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Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Standard Mode Register ................................................................................................................................. 171
Burst Length ............................................................................................................................................. 171
Burst Type ................................................................................................................................................ 172
CAS Latency ............................................................................................................................................. 173
Operating Mode ........................................................................................................................................ 174
Extended Mode Register ................................................................................................................................ 175
Temperature-Compensated Self Refresh ................................................................................................... 175
Partial-Array Self Refresh .......................................................................................................................... 176
Output Drive Strength ............................................................................................................................... 176
Status Read Register ...................................................................................................................................... 177
Bank/Row Activation ..................................................................................................................................... 179
READ Operation ............................................................................................................................................ 180
WRITE Operation .......................................................................................................................................... 191
PRECHARGE Operation ................................................................................................................................. 203
Auto Precharge .............................................................................................................................................. 203
Concurrent Auto Precharge ....................................................................................................................... 204
AUTO REFRESH Operation ............................................................................................................................ 209
SELF REFRESH Operation ............................................................................................................................. 210
Power-Down ................................................................................................................................................. 211
Deep Power-Down ................................................................................................................................... 213
Clock Change Frequency ............................................................................................................................... 215
Revision History ............................................................................................................................................ 216
Rev. F, Preliminary – 03/10 ........................................................................................................................ 216
Rev. E, Preliminary – 02/10 ........................................................................................................................ 216
Rev. D, Preliminary – 01/10 ........................................................................................................................ 216
Rev. C, Preliminary – 12/09 ........................................................................................................................ 216
Rev. B, Preliminary – 10/09 ........................................................................................................................ 216
Rev. A, Preliminary – 7/09 .......................................................................................................................... 217
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. F 03/10
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.