ADV7480.pdf 데이터시트 (총 19 페이지) - 파일 다운로드 ADV7480 데이타시트 다운로드

No Preview Available !

Data Sheet
Dual Mode HDMI/MHL Receiver
ADV7480
FEATURES
Mobile High-Definition Link (MHL) capable receiver
High-bandwidth Digital Content Protection (HDCP)
authentication and decryption support
75 MHz maximum pixel clock frequency, allowing HDTV
formats up to 720p/1080i at 60 Hz
24 bits per pixel mode supported
HDCP repeater support, up to 25 KSVs supported
Adaptive TMDS equalizer
High-Definition Multimedia Interface (HDMI) capable
receiver
HDCP authentication and decryption support
162 MHz maximum pixel clock frequency, allowing HDTV
formats up to 1080p and display resolutions up to UXGA
(1600 × 1200 at 60 Hz)
HDCP repeater support, up to 25 KSVs supported
Integrated CEC controller, CEC 1.4 compatible
Adaptive TMDS equalizer
5 V detect and Hot Plug assert
Component video processor
Any-to-any 3 × 3 color space conversion (CSC) matrix
Contrast/brightness/hue/saturation video adjustment
Timing adjustments controls for horizontal sync
(HS)/vertical sync (VS)/data enable (DE) timing
Video mute function
Serial digital audio output interface
HDMI/MHL audio extraction support
Advanced audio muting feature
I2S-compatible, left justified and right justified audio
output modes
8-channel TDM output mode available
Mobile Industry Processor Interface (MIPI) Camera Serial
Interface 2 (CSI-2) transmitter
4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing
options for HDMI/MHL/digital input port sources
8-bit digital input/output port
General
2-wire serial microprocessor unit (MPU) interface (I2C
compatible)
−40°C to +85°C temperature grade
100-ball, 9 mm × 9 mm, RoHS-compliant CSP_BGA package
Qualified for automotive applications
APPLICATIONS
Portable devices
Automotive infotainment (head unit and rear seat
entertainment systems)
HDMI repeaters and video switches
RXCP/RXCN
RX0P/RX0N
RX1P/RX1N
RX2P/RX2N
DDC_SCL/
CD_PULLU P
DDC_SD A
HPD/CBUS
CD_SENSE
CEC
RX_5V/VBUS
VBUS_EN
LLC
P0 TO P7
FUNCTIONAL BLOCK DIAGRAM
ADV7480
SPI
SLAVE
MHL_SENSE
CBUS
DDC
HDMI/MHL
RECEIVER
CEC
HPD
EDID RAM
HDCP
8-BIT TTL
INPUT/OUTPUT
AUDIO
PROCESSOR
COMPONENT
PROCESSOR
(CP)
Figure 1.
I2C
SLAVE
INTERRUPTS
CONTROLLER
AUDIO
OUTPUT
FORMATTER
4-LANE
MIPI CSI-2
TRANSMITTER
SPI_MISO
SPI_MOSI
SPI_SCLK
SPI_CS
ALSB
SCLK
SDATA
INTRQ1 TO
INTRQ3
I2S_MCLK
I2S_LRCLK
I2S_SCLK
I2S_SDATA
CLKAP/CLKAN
DA0P/DA0N TO
DA3P/DA3N
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

No Preview Available !

ADV7480
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Detailed Functional Block Diagram .............................................. 4
Specifications..................................................................................... 5
Electrical Characteristics ............................................................. 5
MIPI Video Output Specifications............................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Power Supply Recommendation................................................... 16
REVISION HISTORY
6/14—Revision 0: Initial Version
Data Sheet
Power-Up Sequence ................................................................... 16
Power-Down Sequence.............................................................. 16
Theory of Operation ...................................................................... 17
Combined HDMI/MHL Receiver............................................ 17
MHL Receiver............................................................................. 17
HDMI Receiver........................................................................... 17
Component Processor ............................................................... 18
8-Bit Digital Input/Output Port ............................................... 18
Audio Processing........................................................................ 18
MIPI CSI-2 Transmitter ............................................................ 18
Interrupts..................................................................................... 18
Outline Dimensions...................................................................... 19
Ordering Guide .......................................................................... 19
Automotive Products ................................................................. 19
Rev. 0 | Page 2 of 19

No Preview Available !

Data Sheet
GENERAL DESCRIPTION
The ADV7480 is a combined HDMI®/MHL® receiver targeted at
connectivity enabled head units requiring a wired, uncompressed
digital audio/video link from smartphones and other consumer
electronics devices to support streaming and integration of
cloud-based multimedia content and applications into an
automotive infotainment system.
The ADV7480 MHL 2.1 capable receiver supports a maximum
pixel clock frequency of 75 MHz, allowing resolutions up to
720p/1080i at 60 Hz in 24-bit mode. The ADV7480 features a
link control bus (CBUS) that handles the link layer, translation
layer, CBUS electrical discovery, and display data channel
(DDC) commands. The implementation of the MHL sideband
channel (MSC) commands by the system processor can be
handled either by the I2C bus, or via a dedicated serial
peripheral interface (SPI) bus. A dedicated interrupt pin
(INTRQ3) is available to indicate that events related to CBUS
have occurred.
The ADV7480 also features an enable pin (VBUS_EN) to
dynamically enable or disable the output of a voltage regulator,
which provides a 5 V voltage bus (VBUS) signal to the MHL
source.
The ADV7480 HDMI capable receiver supports a maximum
pixel clock frequency of 162 MHz, allowing HDTV formats up
to 1080p, and display resolutions up to UXGA (1600 × 1200 at
60 Hz). The device integrates a consumer electronics control
(CEC) controller that supports the capability discovery and
control (CDC) feature. The HDMI input port has dedicated 5 V
detect and Hot Plug™ assert pins.
The HDMI/MHL receiver includes an adaptive transition
minimized differential signaling (TMDS) equalizer that ensures
robust operation of the interface with long cables.
The ADV7480 single receiver port is capable of accepting both
HDMI and MHL electrical signals. Automatic detection
between HDMI and MHL is achieved by using cable impedance
detection through the CD_SENSE pin.
ADV7480
The ADV7480 contains a component processor (CP) that
processes the video signals from the HDMI/MHL receiver. It
provides features such as contrast, brightness, and saturation
adjustments, as well as free run and timing adjustment controls
for HS/VS/DE timing.
The ADV7480 features an 8-bit digital input/output port,
supporting input and output video resolutions up to 720p/1080i
in both the 8-bit interleaved 4:2:2 SDR and DDR modes.
To enable glueless interfacing of these video input sources to the
latest generation of infotainment system on chips (SoCs), the
ADV7480 features a MIPI® CSI-2 transmitter. The four-lane
transmitter provides four data lanes, two data lanes, and one
data lane muxing options, and can be used to output video from
the HDMI receiver, the MHL receiver, and the digital input
port.
The ADV7480 offers a flexible audio output port for audio data
extracted from the MHL or HDMI streams. The HDMI/MHL
receiver has advanced audio functionality, such as a mute
controller that prevents audible extraneous noise in the audio
output. Additionally, the ADV7480 can be set to output time
division multiplexing (TDM) serial audio, which allows the
transmission of eight multiplexed serial audio channels on a
single audio output interface port.
The ADV7480 is programmed via a 2-wire, serial, bidirectional
port (I2C compatible).
Fabricated in an advanced CMOS process, the ADV7480 is
available in a 9 mm × 9 mm, RoHS-compliant, 100-ball
CSP_BGA package and is specified over the −40°C to +85°C
temperature range.
The ADV7480 is offered in automotive and industrial versions.
Rev. 0 | Page 3 of 19

No Preview Available !

ADV7480
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
XTALP
XTALN
SCLK
SDATA
ALSB
RESET
SPI_MISO
SPI_MOSI
SPI_SCLK
SPI_CS
VBUS_EN
CD_SENSE
HPD/CBUS
RX_5V/VBUS
CEC
DDC_SDA
DDC_SCL/
CD_PULLUP
RXCP/RXCN
RX0P/RX0N
RX1P/RX1N
RX2P/RX2N
LLC
P0
P1
P2
P3
P4
P5
P6
P7
CLOCK
PROCESSING
BLOCK
I2C SLAVE/
CONTROL
SPI
SLAVE
CBUS
CONTROLLER
ADV7480
GENERAL
INTERRUPTS
CONTROLLER
CBUS
INTERRUPTS
CONTROLLER
MHL LINK
DISCOVERY
BLOCK
5V DETECT AND
HPD PIN
CONTROLLER
CEC
CONTROLLER
EDID/
REPEATER
CONTROLLER
HDCP
KEYS
HDCP
ENGINE
PACKET/
INFOFRAME
MEMORY
PACKET
PROCESSOR
AUDIO
PROCESSOR
AUDIO OUTPUT
FORMATTER
PLL
EQUALIZER
SAMPLER
HDMI/MHL
PROCESSOR
COLOR
SPACE
CONVERSION
COMPONENT
PROCESSOR
(CP)
8-BIT
TO
6-BIT
DITHER
BLOCK
8-BIT
DIGITAL
INPUT/
OUTPUT
PORT
MIPI CSI-2
TRANSMITTER A
CSI-2 Tx D-PHY Tx
INTRQ1
INTRQ2
INTRQ3
I2S_MCLK
I2S_LRCLK
I2S_SCLK
I2S_SDATA
CLKAP/CLKAN
DA0P/DA0N
DA1P/DA1N
DA2P/DA2N
DA3P/DA3N
Figure 2.
Rev. 0 | Page 4 of 19

No Preview Available !

Data Sheet
ADV7480
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 1.
Parameter
DIGITAL INPUTS1
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance2
CRYSTAL INPUT
Input High Voltage
Input Low Voltage
DIGITAL OUTPUTS1
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance2
POWER REQUIREMENTS
Digital Power Supply
HDMI/MHL Terminator Supply
HDMI/MHL Comparator Supply
PLL Power Supply
MIPI Transmitter Power Supply
Digital Input/Output Power Supply1
Analog Power Supply
CURRENT CONSUMPTION1, 2, 3, 4
Digital Supply Current
HDMI Input
MHL Input
8-Bit Digital Input
HDMI/MHL Terminator Supply Current
HDMI Input
MHL Input
8-Bit Digital Input
HDMI/MHL Comparator Supply Current
HDMI Input
MHL Input
8-Bit Digital Input
PLL Supply Current
HDMI Input
MHL Input
8-Bit Digital Input
MIPI Transmitters Supply Current
HDMI Input
MHL Input
8-Bit Digital Input
Symbol
VIH
VIL
IIN
CIN
VIH
VIL
VOH
VOL
ILEAK
COUT
DVDD
TVDD
CVDD
PVDD
MVDD
DVDDIO
AVDD
IDVDD
ITVDD
ICVDD
IPVDD
IMVDD
Test Conditions/Comments
SCLK, SDATA, RESET, ALSB, SPI_CS, SPI_SCLK,
SPI_MOSI, LLC, and P0 to P7
DVDDIO = 3.14 V to 3.46 V
DVDDIO = 3.14 V to 3.46 V
XTALP
XTALP
LLC, P0 to P7, I2S_MCLK, I2S_SCLK, I2S_LRCLK,
I2S_SDATA, SPI_MISO, SDATA, INTRQ1 to INTRQ3
(when configured to drive when active), and
VBUS_EN
DVDDIO = 3.14 V to 3.46 V and ISOURCE = 0.4 mA
DVDDIO = 3.14 V to 3.46 V and ISINK = 3.2 mA
3.3 V operation
Min Typ Max Unit
2V
0.8 V
−10 +10 µA
10 pF
1.2 V
0.4 V
2.4
10
V
0.4 V
µA
20 pF
1.71 1.8
3.14 3.3
1.71 1.8
1.71 1.8
1.71 1.8
3.14 3.3
1.71 1.8
1.89 V
3.46 V
1.89 V
1.89 V
1.89 V
3.46 V
1.89 V
204
68.1
93.5
32.5
40
35
24.4
0.7
92
63.9
55.9
0.1
39
29.2
29.3
27.9
62
45.7
38.5
38.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0 | Page 5 of 19