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MX25L1605D
MX25L3205D
MX25L6405D
FEATURES
16M-BIT [x 1 / x 2] CMOS SERIAL FLASH
32M-BIT [x 1 / x 2] CMOS SERIAL FLASH
64M-BIT [x 1 / x 2] CMOS SERIAL FLASH
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure
32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure
64M:67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O read mode) structure
• 512 Equal Sectors with 4K byte each (16Mb)
1024 Equal Sectors with 4K byte each (32Mb)
2048 Equal Sectors with 4K byte each (64Mb)
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each (16Mb)
64 Equal Blocks with 64K byte each (32Mb)
128 Equal Blocks with 64K byte each (64Mb)
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)
- Serial clock of two I/O read mode : 50MHz (15pF + TTL Load), which is equivalent to 100MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 60ms(typ.) /sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip for
16Mb, 25s(typ.) for 32Mb, and 50s(typ.) for 64Mb
• Low Power Consumption
- Low active read current: 25mA(max.) at 86MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
- Deep power-down mode 1uA (typical)
• Typical 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1290
1 REV. 1.4, OCT. 01, 2008

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MX25L1605D
MX25L3205D
MX25L6405D
Status Register Feature
Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- Both REMS and REMS2 commands for 1-byte manufacturer ID and 1-byte device ID
HARDWARE FEATURES
SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO Output
- Serial Data Output
• WP#/ACC pin
- Hardware write protection and program/erase acceleration
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 16-pin SOP (300mil)
- 8-land WSON (8x6mm or 6x5mm)
- 8-pin SOP (200mil, 150mil)
- 8-pin PDIP (300mil)
- 8-land USON (4x4mm)
- All Pb-free devices are RoHS Compliant
ALTERNATIVE
• Security Serial Flash (MX25L1615D/MX25L3215D/MX25L6415D) may provides additional protection features for op-
tion.The datasheet is provided under NDA.
GENERAL DESCRIPTION
The MX25L1605D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it is in
two I/O read mode, the structure becomes 8,388,608 bits x 2. The MX25L3205D are 33,554,432 bit serial Flash memory,
which is configured as 4,194,304 x 8 internally. When it is in two I/O read mode, the structure becomes 16,772,216 bits
x 2. The MX25L6405D are 67,108,864 bit serial Flash memory, which is configured as 8,388,608 x 8 internally. When it
is in two I/O read mode, the structure becomes 33,554,432 bits x 2. (please refer to the "Two I/O Read mode" section).
The MX25L1605D/3205D/6405D feature a serial peripheral interface and software protocol allowing operation on a simple
3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output.
The MX25L1605D/3205D/6405D provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified
page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis,
or word basis for Continuously program mode, and erase command is executes on sector (4K-byte), or block (64K-byte),
or whole chip basis.
P/N: PM1290
REV. 1.4, OCT. 01, 2008
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MX25L1605D
MX25L3205D
MX25L6405D
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for more
details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.
The MX25L1605D/3205D/6405D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even
after typical 100,000 program and erase cycles.
Table 1. Additional Feature Comparison
Additional
Featu-
res
Part Name
Protection and Security
Flexible
Block
protection
(BP0-BP3)
512-bit
secured OTP
Read
Performance
2 I/O Read
(50MHz)
Device ID
(command :
AB hex)
MX25L1605D
V
V
V 14 (hex)
Identifier
Device ID
(command :
90 hex)
Device ID
(command :
EF hex)
RDID
(command:
9F hex)
C2 14 (hex)
(if ADD=0)
C2 14 (hex)
(if ADD=0) C2 20 15 (hex)
MX25L3205D
V
V
C2 15 (hex) C2 15 (hex)
V
15 (hex)
(if ADD=0)
(if ADD=0) C2 20 16 (hex)
MX25L6405D
V
V
C2 16 (hex) C2 16 (hex)
V
16 (hex)
(if ADD=0)
(if ADD=0) C2 20 17 (hex)
P/N: PM1290
REV. 1.4, OCT. 01, 2008
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PIN CONFIGURATIONS
16-PIN SOP (300mil)
HOLD#
VCC
NC
NC
NC
NC
CS#
SO/SIO1
1
2
3
4
5
6
7
8
16 SCLK
15 SI/SIO0
14 NC
13 NC
12 NC
11 NC
10 GND
9 WP#/ACC
MX25L1605D
MX25L3205D
MX25L6405D
8-PIN SOP (200mil, 150mil)
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8 VCC
7 HOLD#
6 SCLK
5 SI/SIO0
8-LAND WSON (8x6mm, 6x5mm), USON (4x4mm)
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8 VCC
7 HOLD#
6 SCLK
5 SI/SIO0
8-PIN PDIP (300mil)
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8 VCC
7 HOLD#
6 SCLK
5 SI/SIO0
PACKAGE OPTIONS
150mil 8-SOP
200mil 8-SOP
300mil 16-SOP
300mil 8-PDIP
6x5mm WSON
8x6mm WSON
4x4mm USON
16M
V
V
V
V
V
V
32M 64M
V
VV
V
V
V
V
PIN DESCRIPTION
SYMBOL
CS#
SI/SIO0
SO/SIO1
SCLK
WP#/ACC
HOLD#
VCC
GND
DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O)/ Serial Data
Input & Output (for 2xI/O read mode)
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O read mode)
Clock Input
Write protection: connect to GND ;
9.5~10.5V for program/erase
acceleration: connect to 9.5~10.5V
Hold, to pause the device without
deselecting the device
+ 3.3V Power Supply
Ground
P/N: PM1290
REV. 1.4, OCT. 01, 2008
4

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BLOCK DIAGRAM
MX25L1605D
MX25L3205D
MX25L6405D
Address
Generator
Memory Array
SI/SIO0
SO/SIO1
CS#,
WP#/ACC,
HOLD#
SCLK
Page Buffer
Data
Register
SRAM
Buffer
Mode
Logic
State
Machine
Y-Decoder
HV
Generator
Sense
Amplifier
Clock Generator
Output
Buffer
P/N: PM1290
REV. 1.4, OCT. 01, 2008
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