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Single-Phase PWM Regulator for IMVP-6.5™ Mobile
CPUs and GPUs
ISL62881C, ISL62881D
The ISL62881C provides a complete solution for
microprocessor and graphic processor core power supply
with it’s integrated gate drive. Based on Intersil’s Robust
Ripple regulator (R3™) technology, the PWM modulator
compared to traditional modulators, has faster transient
settling time, variable switching frequency during load
transients and has improved light load efficiency with its
ability to automatically change switching frequency.
Fully compliant with IMVP6.5™, the ISL62881C is easily
configurable as a CPU or graphics VCORE controllers by
offering: responds to DPRSLPVR signals by
entering/exiting diode emulations mode; reports
regulator output current via the IMON pin; senses
current by using a discrete resistor or the inductor;
over-temperature thermal compensation of DCR, using a
single NTC thermistor; differential sensing to accurately
monitor and adjust processor die voltage; minimizes
body diode conduction loss in diode emulation mode with
it’s adaptive body diode conduction time.
Need to aggressively reduce the output capacitor? The
overshoot reduction function is user-selectable and can
be disabled for those concerned about increased system
thermal stress.
Maintaining all the ISL62881C functions, the ISL62881D
offers VR_TT# function for thermal throttling control. It
also offers the split LGATE function to further improve
light load efficiency.
Features
• Precision Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Current Monitor
• Differential Remote Voltage Sensing
• Integrated Gate Driver
• Split LGATE Driver to Increase Light-Load Efficiency
(For ISL62881D)
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 28 Ld 4x4 or 32 Ld 5x5 TQFN
Package
Applications
• Notebook Core Voltage Regulator
• Notebook GPU Voltage Regulator
Related Literature
• See AN1552 for Evaluation Board Application Note
“ISL62881CCPUEVAL2Z User Guide”
• See AN1553 for Evaluation Board Application Note
“ISL62881CGPUEVAL2Z User Guide”
Load Line Regulation
0.91
0.90
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
0
VIN = 19V
VIN = 12V
VIN = 8V
2 4 6 8 10 12 14 16 18 20 22
IOUT (A)
March 8, 2010
FN7596.0
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL62881C, ISL62881D
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62881CHRTZ
62881C HRTZ
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62881CIRTZ
62881C IRTZ
-40 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62881DHRTZ
62881D HRTZ
-10 to +100
32 Ld 5x5 TQFN
L32.5x5E
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62881C, ISL62881D. For more information on
MSL please see techbrief TB363.
Pin Configurations
ISL62881C
(28 LD TQFN)
TOP VIEW
ISL62881D
(32 LD TQFN)
TOP VIEW
28 27 26 25 24 23 22
CLK_EN# 1
PGOOD 2
RBIAS 3
VW 4
COMP 5
FB 6
VSEN 7
GND PAD
(BOTTOM)
21 VID1
20 VID0
19 VCCP
18 LGATE
17 VSSP
16 PHASE
15 UGATE
8 9 10 11 12 13 14
32 31 30 29 28 27 26 25
PGOOD 1
RBIAS 2
VR_TT# 3
NTC 4
GND 5
VW 6
COMP 7
FB 8
GND PAD
(BOTTOM)
24 VID1
23 VID0
22 VCCP
21 LGATEb
20 LGATEa
19 VSSP
18 PHASE
17 UGATE
9 10 11 12 13 14 15 16
Pin Function Description
ISL62881C ISL62881D
1 32
21
32
-3
-4
-5
SYMBOL
CLK_EN#
PGOOD
RBIAS
VR_TT#
NTC
GND
DESCRIPTION
Open drain output to enable system PLL clock. It goes low 13 switching cycles after
VCORE is within 10% of VBOOT.
Power-Good open-drain output indicating when the regulator is able to supply
regulated voltage. Pull up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
A resistor to GND sets internal current reference. A 147kΩ resistor sets the controller
for CPU core application and a 47kΩ resistor sets the controller for GPU core
application.
Thermal overload output indicator.
Thermistor input to VR_TT# circuit.
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND
pin.
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ISL62881C, ISL62881D
Pin Function Description (Continued)
ISL62881C ISL62881D
46
57
68
79
8 10
SYMBOL
VW
COMP
FB
VSEN
RTN
DESCRIPTION
A resistor from this pin to COMP programs the switching frequency (8kΩ gives
approximately 300kHz).
This pin is the output of the error amplifier. Also, a resistor across this pin and GND
adjusts the overcurrent threshold.
This pin is the inverting input of the error amplifier.
Remote core voltage sense input. Connect to microprocessor die.
Remote voltage sensing return. Connect to ground at microprocessor die.
9, 10
11
12
13
14
15
16
17
18
-
-
19
11, 12
13
14
15
16
17
18
19
-
20
21
22
ISUM- and Droop current sense input.
ISUM+
VDD
5V bias power.
VIN Power stage supply voltage, used for feed-forward.
IMON
An analog output. IMON outputs a current proportional to the regulator output
current.
BOOT
Connect an MLCC capacitor across the BOOT and the PHASE pin. The boot capacitor
is charged through an internal boot diode connected from the VCCP pin to the BOOT
pin, each time the PHASE pin drops below VCCP minus the voltage dropped across the
internal boot diode.
UGATE
Output of the high-side MOSFET gate driver. Connect the UGATE pin to the gate of the
high-side MOSFET.
PHASE
Current return path for the high-side MOSFET gate driver. Connect the PHASE pin to
the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and
the output inductor.
VSSP
Current return path for the low-side MOSFET gate driver. Connect the VSSP pin to the
source of the low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE pins to the gates of the low-side MOSFET.
LGATE
Output of the low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
LGATEa Output of the low-side MOSFET gate driver that is always active. Connect the LGATEa
pin to the gate of the low-side MOSFET that is active all the time.
LGATEb
Another output of the low-side MOSFET gate driver. This gate driver will be pulled low
when the DPRSLPVR pin logic is high. Connect the LGATEb pin to the gate of the
low-side MOSFET that is idle in deeper sleep mode.
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin.
Decouple with at least 1µF of an MLCC capacitor to the VSSP pin.
20, 21, 22,
23, 24, 25,
26
23, 24, 25,
26, 27, 28
29
VID0,
VID1,
VID2,
VID3,
VID4,
VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
27 30 VR_ON Voltage regulator enable input. A high level logic signal on this pin enables the
regulator.
28 31 DPRSLPVR Deeper sleep enable signal. A high level logic signal on this pin indicates that the
microprocessor is in deeper sleep mode.
pad BOTTOM The bottom pad is electrically connected to the GND pin inside the IC. It should also
be used as the thermal pad for heat removal.
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ISL62881C, ISL62881D
Block Diagram
VIN VSEN
PGOOD CLK_EN#
VDD
VR_ON
DPRSLPVR
RBIAS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
RTN
FB
COMP
VW
IMON
ISUM+
ISUM-
MODE
CONTROL
DAC
AND
SOFT
START
PGOOD
AND
CLK_EN#
LOGIC
6µA 54µA 1.20V
1.24V
PROTECTION FLT
WOC OC
VIN
CLOCK
VDAC
COMP
VW
ISL62881D
ONLY
VR_TT#
NTC
Σ
E/A
Idroop
Imon
CURRENT
SENSE
2.5
X
VIN VDAC
MODULATOR
WOC
COMP
CURRENT
COMPARATORS
60µA
OC
Σ
DRIVER
SHOOT
THROUGH
PROTECTION
DRIVER
DRIVER
BOOT
UGATE
PHASE
VCCP
LGATEA
VSSP
ISL62881C ONLY
LGATEB
ADJ. OCP
THRESHOLD
COMP
ISL62881D
ONLY
GND
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ISL62881C, ISL62881D
Table of Contents
Related Literature . . . . . . . . . . . . . . . . . . . . . . 1
Load Line Regulation . . . . . . . . . . . . . . . . . . . . 1
Pin Function Description . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 6
Gate Driver Timing Diagram. . . . . . . . . . . . . . . 9
Simplified Application Circuits . . . . . . . . . . . . . 9
Theory of Operation . . . . . . . . . . . . . . . . . . . . 12
Multiphase R3™ Modulator .............................. 12
Diode Emulation and Period Stretching.............. 13
Start-up Timing ............................................. 13
Voltage Regulation and Load Line
Implementation ........................................... 14
Differential Sensing ........................................ 16
CCM Switching Frequency ............................... 16
Modes of Operation ........................................16
Dynamic Operation......................................... 16
Protections .................................................... 17
Current Monitor ............................................. 17
Adaptive Body Diode Conduction
Time Reduction ............................................ 18
Overshoot Reduction Function.......................... 18
Key Component Selection . . . . . . . . . . . . . . . . 18
RBIAS ........................................................... 18
Inductor DCR Current-Sensing Network ............ 18
Resistor Current-Sensing Network .................. 20
Overcurrent Protection ................................... 21
Load Line Slope............................................. 21
Current Monitor............................................. 21
Compensator ................................................ 22
Optional Slew Rate Compensation Circuit
for 1-Tick VID Transition ............................... 24
Voltage Regulator Thermal Throttling ............... 24
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . 25
CPU Application Reference Design
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . 29
GPU Application Reference Design
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . 30
Typical Performance . . . . . . . . . . . . . . . . . . . . 32
Revision History . . . . . . . . . . . . . . . . . . . . . . . 35
Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing
L28.4x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Outline Drawing
L32.5x5E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 FN7596.0
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