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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F32G08ABAAA, MT29F64G08AFAAA, MT29F128G08A[J/K/M]AAA
MT29F256G08AUAAA, MT29F32G08ABCAB, MT29F64G08AECAB
MT29F128G08A[K/M]CAB, MT29F256G08AUCAB
Features
• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 8640 bytes (8192 + 448 bytes)
– Block size: 128 pages (1024K + 56K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 32Gb: 4096 blocks;
64Gb: 8192 blocks;
128Gb: 16,384 blocks;
256Gb: 32,786 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 5
– Clock rate: 10ns (DDR)
– Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
tRC/tWC: 20ns (MIN)
– Read/write throughput per pin: 50 MT/s
• Array performance
– Read page: 35µs (MAX)
– Program page: 350µs (TYP)
– Erase block: 1.5ms (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 114).
• RESET (FFh) required as first command after pow-
er-on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: JESD47G compliant; see qualifi-
cation report
– Endurance: 60,000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 52-pad LGA
– 48-pin TSOP
– 100-ball BGA
– 132-ball BGA
Note: 1. The ONFI 2.2 specification is available at
www.onfi.org.
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M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 32G 08 A B A A A WP
Micron Technology
NAND Flash
29F = NAND Flash memory
Density
32G = 32Gb
64G = 64Gb
128G = 128Gb
256G = 256Gb
Device Width
08 = 8 bits
Level
Bit/Cell
A 1-bit
Classification
Die # of CE# # of R/B# I/O
B1
1
1 Common
E2
2
2 Separate
F2
2
2 Common
J4
2
2 Common
K4
2
2 Separate
M4
4
4 Separate
U8
4
4 Separate
Operating Voltage Range
A = VCC: 3.3V (2.7–3.6V), VCCQ: 3.3V (2.7–3.6V)
C = VCC: 3.3V (2.7–3.6V), VCCQ: 1.8V (1.7–1.95V)
Note: 1. Pb-free package.
Z ES :A
Design Revision
A = First revision
Production Status
Blank = Production
ES = Engineering sample
Reserved for Future Use
Blank
Wafer Process Applied
Blank = Polyimide Process Not Applied
Z = Polyimide Process Applied
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade (synchronous mode only)
-10 = 200 MT/s
Package Code
C5 = 52-pad VLGA 14mm x 18mm x 1.0mm1
H1 = 100-ball VBGA 12mm x 18mm x 1.0mm1
H2 = 100-ball TBGA 12mm x 18mm x 1.2mm1
H3 = 100-ball LBGA 12mm x 18mm x 1.4mm1
J1 = 132-ball VBGA 12mm x 18mm x 1.0mm1
J2 = 132-ball TBGA 12mm x 18mm x 1.2mm1
J3 = 132-ball LBGA 12mm x 18mm x 1.4mm1
WP = 48-pin TSOP1 (CPL)
Interface
A = Async only
B = Sync/Async
Generation Feature Set
A = First set of device features
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M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Features
Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ....................................................................................................................................... 15
Architecture ................................................................................................................................................... 23
Device and Array Organization ........................................................................................................................ 24
Bus Operation – Asynchronous Interface ......................................................................................................... 32
Asynchronous Enable/Standby ................................................................................................................... 32
Asynchronous Bus Idle ............................................................................................................................... 32
Asynchronous Commands .......................................................................................................................... 33
Asynchronous Addresses ............................................................................................................................ 34
Asynchronous Data Input ........................................................................................................................... 35
Asynchronous Data Output ......................................................................................................................... 36
Write Protect .............................................................................................................................................. 37
Ready/Busy# .............................................................................................................................................. 37
Bus Operation – Synchronous Interface ........................................................................................................... 42
Synchronous Enable/Standby ..................................................................................................................... 43
Synchronous Bus Idle/Driving .................................................................................................................... 43
Synchronous Commands ............................................................................................................................ 44
Synchronous Addresses .............................................................................................................................. 45
Synchronous DDR Data Input ..................................................................................................................... 46
Synchronous DDR Data Output .................................................................................................................. 47
Write Protect .............................................................................................................................................. 49
Ready/Busy# .............................................................................................................................................. 49
Device Initialization ....................................................................................................................................... 50
Activating Interfaces ....................................................................................................................................... 52
Activating the Asynchronous Interface ........................................................................................................ 52
Activating the Synchronous Interface .......................................................................................................... 52
Command Definitions .................................................................................................................................... 54
Reset Operations ............................................................................................................................................ 56
RESET (FFh) ............................................................................................................................................... 56
SYNCHRONOUS RESET (FCh) .................................................................................................................... 57
RESET LUN (FAh) ....................................................................................................................................... 58
Identification Operations ................................................................................................................................ 59
READ ID (90h) ............................................................................................................................................ 59
READ ID Parameter Tables .......................................................................................................................... 60
READ PARAMETER PAGE (ECh) .................................................................................................................. 61
Parameter Page Data Structure Tables ..................................................................................................... 62
READ UNIQUE ID (EDh) ............................................................................................................................ 72
Configuration Operations ............................................................................................................................... 73
SET FEATURES (EFh) .................................................................................................................................. 73
GET FEATURES (EEh) ................................................................................................................................. 74
Status Operations ........................................................................................................................................... 78
READ STATUS (70h) ................................................................................................................................... 79
READ STATUS ENHANCED (78h) ................................................................................................................ 80
Column Address Operations ........................................................................................................................... 81
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 81
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 82
CHANGE WRITE COLUMN (85h) ................................................................................................................ 83
CHANGE ROW ADDRESS (85h) ................................................................................................................... 84
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M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Features
Read Operations ............................................................................................................................................. 86
READ MODE (00h) ..................................................................................................................................... 88
READ PAGE (00h-30h) ................................................................................................................................ 89
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 90
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 91
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 93
READ PAGE MULTI-PLANE (00h-32h) ......................................................................................................... 94
Program Operations ....................................................................................................................................... 96
PROGRAM PAGE (80h-10h) ......................................................................................................................... 96
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 98
PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................ 100
Erase Operations ........................................................................................................................................... 102
ERASE BLOCK (60h-D0h) ........................................................................................................................... 102
ERASE BLOCK MULTI-PLANE (60h-D1h) ................................................................................................... 103
Copyback Operations .................................................................................................................................... 104
COPYBACK READ (00h-35h) ...................................................................................................................... 105
COPYBACK PROGRAM (85h–10h) .............................................................................................................. 106
COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 106
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 107
One-Time Programmable (OTP) Operations ................................................................................................... 108
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 109
PROTECT OTP AREA (80h-10h) .................................................................................................................. 110
READ OTP PAGE (00h-30h) ........................................................................................................................ 111
Multi-Plane Operations ................................................................................................................................. 112
Multi-Plane Addressing ............................................................................................................................. 112
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 113
Error Management ........................................................................................................................................ 114
Output Drive Impedance ............................................................................................................................... 115
AC Overshoot/Undershoot Specifications ....................................................................................................... 118
Synchronous Input Slew Rate ......................................................................................................................... 119
Output Slew Rate ........................................................................................................................................... 120
Electrical Specifications ................................................................................................................................. 121
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 124
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) ................................... 125
Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 125
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 126
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 128
Electrical Specifications – Array Characteristics .............................................................................................. 131
Asynchronous Interface Timing Diagrams ...................................................................................................... 132
Synchronous Interface Timing Diagrams ........................................................................................................ 143
Revision History ............................................................................................................................................ 165
Rev. F Production – 5/12 ............................................................................................................................ 165
Rev. E Production – 4/12 ............................................................................................................................ 165
Rev. D Production – 6/11 ............................................................................................................................ 165
Rev. C – 12/10 ............................................................................................................................................ 165
Rev. B – 7/10 .............................................................................................................................................. 165
Rev. A – 2/10 .............................................................................................................................................. 166
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M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
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32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Features
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions .............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 31
Table 3: Asynchronous Interface Mode Selection ............................................................................................ 32
Table 4: Synchronous Interface Mode Selection .............................................................................................. 42
Table 5: Command Set .................................................................................................................................. 54
Table 6: Read ID Parameters for Address 00h .................................................................................................. 60
Table 7: Read ID Parameters for Address 20h .................................................................................................. 60
Table 8: Parameter Page Data Structure .......................................................................................................... 62
Table 9: Feature Address Definitions .............................................................................................................. 73
Table 10: Feature Address 01h: Timing Mode .................................................................................................. 75
Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength .............................................. 76
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 76
Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 77
Table 14: Status Register Definition ................................................................................................................ 78
Table 15: OTP Area Details ............................................................................................................................ 109
Table 16: Error Management Details ............................................................................................................. 114
Table 17: Output Drive Strength Conditions (VCCQ = 1.7–1.95V) ...................................................................... 115
Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) ........................................................... 115
Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 116
Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 116
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch ..................................................................... 117
Table 22: Asynchronous Overshoot/Undershoot Parameters .......................................................................... 118
Table 23: Synchronous Overshoot/Undershoot Parameters ............................................................................ 118
Table 24: Test Conditions for Input Slew Rate ................................................................................................ 119
Table 25: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 119
Table 26: Test Conditions for Output Slew Rate .............................................................................................. 120
Table 27: Output Slew Rate (VCCQ = 1.7–1.95V) ............................................................................................... 120
Table 28: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 120
Table 29: Absolute Maximum Ratings by Device ............................................................................................ 121
Table 30: Recommended Operating Conditions ............................................................................................. 121
Table 31: Valid Blocks per LUN ...................................................................................................................... 121
Table 32: Capacitance: 100-Ball BGA Package ................................................................................................ 122
Table 33: Capacitance: 132-Ball BGA Package ................................................................................................ 123
Table 34: Capacitance: 48-Pin TSOP Package ................................................................................................. 123
Table 35: Capacitance: 52-Pad LGA Package .................................................................................................. 123
Table 36: Test Conditions .............................................................................................................................. 124
Table 37: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 124
Table 38: DC Characteristics and Operating Conditions (Synchronous Interface) ............................................ 125
Table 39: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 125
Table 40: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 126
Table 41: AC Characteristics: Asynchronous Command, Address, and Data ..................................................... 126
Table 42: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 128
Table 43: Array Characteristics ...................................................................................................................... 131
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M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.