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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F64G08CBAA[A/B], MT29F128G08C[E/F]AAA, MT29F128G08CFAAB,
MT29F256G08C[J/K/M]AAA, MT29F256G08CJAAB, MT29F512G08CUAAA,
MT29F64G08CBCAB, MT29F128G08CECAB, MT29F256G08C[K/M]CAB,
MT29F512G08CUCAB
Features
Open NAND Flash Interface (ONFI) 2.2-compliant1
Multiple-level cell (MLC) technology
Organization
Page size x8: 8640 bytes (8192 + 448 bytes)
Block size: 256 pages (2048K + 112K bytes)
Plane size: 2 planes x 2048 blocks per plane
Device size: 64Gb: 4096 blocks;
128Gb: 8192 blocks;
256Gb: 16,384 blocks;
512Gb: 32,786 blocks
Synchronous I/O performance
Up to synchronous timing mode 52
Clock rate: 10ns (DDR)
Read/write throughput per pin: 200 MT/s
Asynchronous I/O performance
Up to asynchronous timing mode 5
tRC/tWC: 20ns (MIN)
Up to asynchronous timing mode 5
Read/write throughput per pin: 50 MT/s
Array performance
Read page: 75µs (MAX)
Program page: 1300µs (TYP)
Erase block: 3.8ms (TYP)
Operating Voltage Range
VCC: 2.7–3.6V
VCCQ: 1.7–1.95V, 2.7–3.6V
Command set: ONFI NAND Flash Protocol
Advanced Command Set
Program cache
Read cache sequential
Read cache random
One-time programmable (OTP) mode
Multi-plane commands
Multi-LUN operations
Read unique ID
Copyback
First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 109).
RESET (FFh) required as first command after power-
on
Operation status byte provides software method for
detecting
Operation completion
Pass/fail condition
Write-protect status
Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
Copyback operations supported within the plane
from which data is read
Quality and reliability
Data retention: JESD47G compliant; see qualifica-
tion report
Endurance: 3000 PROGRAM/ERASE cycles
Operating temperature:
Commercial: 0°C to +70°C
Industrial (IT): –40ºC to +85ºC
Package
52-pad LGA
48-pin TSOP
100-ball BGA
Notes:
1. The ONFI 2.2 specification is available at
www.onfi.org.
2. BGA devices up to Synchronous timing
mode 5. TSOP devices up to Synchronous tim-
ing mode 4.
PDF: 09005aef83d2277a
Rev. E 3/11 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 64G 08 C B A A A WP
Micron Technology
NAND Flash
29F = NAND Flash memory
Density
64G = 64Gb
128G = 128Gb
256G = 256Gb
512G = 512Gb
Device Width
08 = 8 bits
Level
Bit/Cell
C 2-bit
Classification
Die # of CE# # of R/B# I/O
B1
1
1 Common
E2
2
2 Separate
F2
2
2 Common
J4
2
2 Common
K4
2
2 Separate
M4
4
4 Separate
U8
4
4 Separate
Operating Voltage Range
A = VCC: 3.3V (2.7–3.6V), VCCQ: 3.3V (2.7–3.6V)
C = VCC: 3.3V (2.7–3.6V), VCCQ: 1.8V (1.7–1.95V)
Note: 1. Pb-free package.
ES :A
Design Revision
A = First revision
Production Status
Blank = Production
ES = Engineering sample
Reserved for Future Use
Blank
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade (synchronous mode only)
-12 = 166 MT/s
-10 = 200 MT/s
Package Code
C5 = 52-pad VLGA 14mm x 18mm x 1.0mm1
H1 = 100-ball VBGA 12mm x 18mm x 1.0mm1
H2 = 100-ball TBGA 12mm x 18mm x 1.2mm1
H3 = 100-ball LBGA 12mm x 18mm x 1.4mm1
WP = 48-pin TSOP1 (CPL)
Interface
A = Async only
B = Sync/Async
Generation Feature Set
A = First set of device features
PDF: 09005aef83d2277a
Rev. E 3/11 EN
2 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ...................................................................................................................................... 14
Architecture ................................................................................................................................................... 19
Device and Array Organization ....................................................................................................................... 20
Bus Operation – Asynchronous Interface ........................................................................................................ 27
Asynchronous Enable/Standby ................................................................................................................... 27
Asynchronous Bus Idle ............................................................................................................................... 27
Asynchronous Commands .......................................................................................................................... 28
Asynchronous Addresses ............................................................................................................................ 29
Asynchronous Data Input ........................................................................................................................... 30
Asynchronous Data Output ........................................................................................................................ 31
Write Protect .............................................................................................................................................. 32
Ready/Busy# .............................................................................................................................................. 32
Bus Operation – Synchronous Interface ........................................................................................................... 37
Synchronous Enable/Standby ..................................................................................................................... 38
Synchronous Bus Idle/Driving .................................................................................................................... 38
Synchronous Commands ........................................................................................................................... 39
Synchronous Addresses .............................................................................................................................. 40
Synchronous DDR Data Input ..................................................................................................................... 41
Synchronous DDR Data Output .................................................................................................................. 42
Write Protect .............................................................................................................................................. 44
Ready/Busy# .............................................................................................................................................. 44
Device Initialization ....................................................................................................................................... 45
Activating Interfaces ....................................................................................................................................... 46
Activating the Asynchronous Interface ........................................................................................................ 46
Activating the Synchronous Interface .......................................................................................................... 46
Command Definitions .................................................................................................................................... 48
Reset Operations ............................................................................................................................................ 50
RESET (FFh) ............................................................................................................................................... 50
SYNCHRONOUS RESET (FCh) .................................................................................................................... 51
RESET LUN (FAh) ....................................................................................................................................... 52
Identification Operations ................................................................................................................................ 53
READ ID (90h) ............................................................................................................................................ 53
READ ID Parameter Tables ......................................................................................................................... 54
READ PARAMETER PAGE (ECh) .................................................................................................................. 55
Parameter Page Data Structure Tables ..................................................................................................... 56
READ UNIQUE ID (EDh) ............................................................................................................................ 67
Configuration Operations ............................................................................................................................... 68
SET FEATURES (EFh) ................................................................................................................................. 68
GET FEATURES (EEh) ................................................................................................................................. 69
Status Operations ........................................................................................................................................... 73
READ STATUS (70h) ................................................................................................................................... 74
READ STATUS ENHANCED (78h) ............................................................................................................... 75
Column Address Operations ........................................................................................................................... 76
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 76
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 77
CHANGE WRITE COLUMN (85h) ................................................................................................................ 78
CHANGE ROW ADDRESS (85h) ................................................................................................................... 79
PDF: 09005aef83d2277a
Rev. E 3/11 EN
3 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
Read Operations ............................................................................................................................................. 81
READ MODE (00h) ..................................................................................................................................... 83
READ PAGE (00h-30h) ................................................................................................................................ 84
READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 85
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 86
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 88
READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 89
Program Operations ....................................................................................................................................... 91
PROGRAM PAGE (80h-10h) ........................................................................................................................ 91
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 93
PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................. 95
Erase Operations ............................................................................................................................................ 97
ERASE BLOCK (60h-D0h) ............................................................................................................................ 97
ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 98
Copyback Operations ..................................................................................................................................... 99
COPYBACK READ (00h-35h) ...................................................................................................................... 100
COPYBACK PROGRAM (85h–10h) .............................................................................................................. 101
COPYBACK READ MULTI-PLANE (00h-32h) .............................................................................................. 101
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 102
One-Time Programmable (OTP) Operations ................................................................................................... 103
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 104
PROTECT OTP AREA (80h-10h) .................................................................................................................. 105
READ OTP PAGE (00h-30h) ........................................................................................................................ 106
Multi-Plane Operations ................................................................................................................................. 107
Multi-Plane Addressing ............................................................................................................................. 107
Interleaved Die (Multi-LUN) Operations ........................................................................................................ 108
Error Management ........................................................................................................................................ 109
Shared Pages ................................................................................................................................................. 110
Output Drive Impedance ............................................................................................................................... 112
AC Overshoot/Undershoot Specifications ...................................................................................................... 115
Synchronous Input Slew Rate ........................................................................................................................ 116
Output Slew Rate ........................................................................................................................................... 117
Electrical Specifications ................................................................................................................................. 118
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 120
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) .................................. 121
Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 121
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 122
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 124
Electrical Specifications – Array Characteristics .............................................................................................. 127
Asynchronous Interface Timing Diagrams ...................................................................................................... 128
Synchronous Interface Timing Diagrams ........................................................................................................ 139
Revision History ............................................................................................................................................ 161
Rev. E Production – 3/11 ............................................................................................................................ 161
Rev. D Production – 12/10 ......................................................................................................................... 161
Rev. C – 7/10 ............................................................................................................................................. 161
Rev. B – 2/10 ............................................................................................................................................. 161
Rev. A – 11/09 ............................................................................................................................................ 161
PDF: 09005aef83d2277a
Rev. E 3/11 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 26
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 27
Table 4: Synchronous Interface Mode Selection ............................................................................................. 37
Table 5: Command Set .................................................................................................................................. 48
Table 6: Read ID Parameters for Address 00h ................................................................................................. 54
Table 7: Read ID Parameters for Address 20h .................................................................................................. 54
Table 8: Parameter Page Data Structure ......................................................................................................... 56
Table 9: Feature Address Definitions .............................................................................................................. 68
Table 10: Feature Address 01h: Timing Mode ................................................................................................. 70
Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 71
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 71
Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 72
Table 14: Status Register Definition ............................................................................................................... 73
Table 15: OTP Area Details ........................................................................................................................... 104
Table 16: Error Management Details ............................................................................................................. 109
Table 17: Shared Pages ................................................................................................................................. 110
Table 18: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 112
Table 19: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 112
Table 20: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 113
Table 21: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 113
Table 22: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 114
Table 23: Overshoot/Undershoot Parameters ................................................................................................ 115
Table 24: Test Conditions for Input Slew Rate ................................................................................................ 116
Table 25: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 116
Table 26: Input Slew Rate (VCCQ= 2.7–3.6V) ................................................................................................... 116
Table 27: Test Conditions for Output Slew Rate ............................................................................................. 117
Table 28: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 117
Table 29: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 117
Table 30: Absolute Maximum Ratings by Device ............................................................................................ 118
Table 31: Recommended Operating Conditions ............................................................................................ 118
Table 32: Valid Blocks per LUN ..................................................................................................................... 118
Table 33: Capacitance: 100-Ball BGA Package ................................................................................................ 119
Table 34: Capacitance: 48-Pin TSOP Package ................................................................................................ 119
Table 35: Capacitance: 52-Pad LGA Package .................................................................................................. 119
Table 36: Test Conditions ............................................................................................................................. 120
Table 37: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 120
Table 38: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 121
Table 39: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 121
Table 40: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 122
Table 41: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 122
Table 42: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 124
Table 43: Array Characteristics ..................................................................................................................... 127
PDF: 09005aef83d2277a
Rev. E 3/11 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.