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Micron Confidential and Proprietary
8Gb,16Gb: x8, x16 NAND Flash Memory
Features
NAND Flash Memory
MT29F8G08ABACA, MT29F8G16ABACA, MT29F8G08ABBCA,
MT29F8G16ABBCA, MT29F16G08ADACA, MT29F16G16ADACA,
MT29F16G08ADBCA , MT29F16G16ADBCA
Features
• Open NAND Flash Interface (ONFI) 1.0-compliant1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Page size x16: 2160 words (2048 + 112 words)
– Block size: 64 pages (256K + 14K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 8Gb: 4096 blocks
– Device size: 16Gb: 8192 blocks
• Asynchronous I/O performance
tRC/tWC: 20ns (3.3V), 30ns (1.8V)
• Array performance
– Read page: 25µs
– Program page: 200µs (TYP)
– Erase block: 2ms (TYP)
• Command set: ONFI NAND Flash Protocol
• Advanced command set
– Program page cache mode
– Read page cache mode
– One-time programmable (OTP) mode
– Block lock (1.8V only)
– Programmable drive strength
– Two-plane commands
– Multi-die (LUN) operations
– Read unique ID
– Internal data move
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Ready/Busy# (R/B#) signal provides a hardware
method of detecting operation completion
• WP# signal: Write protect entire device
• First block (block address 00h) is valid when ship-
ped from factory with ECC. For minimum required
ECC, see Error Management.
• RESET (FFh) required as first command after
power-on
• Alternative method of device initialization after
power-up (contact factory)
• Internal data move operations supported within the
plane from which data is read
• Quality and reliability
– Data retention: JESD47G-compliant; see qualifi-
cation report
– Endurance: See qualification report
• Operating voltage range
– VCC: 2.7–3.6V
– VCC: 1.7–1.95V
• Operating temperature
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 48-pin TSOP type 1, CPL2
– 63-ball VFBGA
Notes: 1. The ONFI 1.0 specification is available at
www.onfi.org.
2. CPL = Center parting line
PDF: 09005aef83ea4f61
m71m_8Gb_nand.pdf – Rev. L 1/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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Micron Confidential and Proprietary
8Gb,16Gb: x8, x16 NAND Flash Memory
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Marketing Part Number Chart
MT 29F 8G 08 A B A C A WP xx xx x ES :C
Micron Technology
Product Family
29F = NAND Flash memory
Density
8G = 8Gb
16G = 16Gb
Device Width
08 = 8-bit
16 = 16-bit
Level
A = SLC
Classification
Mark Die nCE RnB I/O Channels
B1
11
1
D2
11
1
Operating Voltage Range
A = 3.3V (2.7–3.6V)
B = 1.8V (1.7–1.95V)
Feature Set
C = Feature set C
Design Revision (shrink)
Production Status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
QS = Qualification sample
Reserved for Future Use
Blank
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade
Blank
Package Code
H4 = 63-ball VFBGA (9 x 11 x 1.0mm)
WP = 48-pin TSOP CPL Type 1
Interface
A = Async only
B = Sync/Async
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m71m_8Gb_nand.pdf – Rev. L 1/12 EN
2 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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Micron Confidential and Proprietary
8Gb,16Gb: x8, x16 NAND Flash Memory
Features
Contents
General Description ......................................................................................................................................... 8
Signal Descriptions ........................................................................................................................................... 8
Signal Assignments ........................................................................................................................................... 9
Package Dimensions ....................................................................................................................................... 12
Architecture ................................................................................................................................................... 14
Device and Array Organization ........................................................................................................................ 15
Bare Die Array Organization ........................................................................................................................ 17
Asynchronous Interface Bus Operation ........................................................................................................... 19
Asynchronous Enable/Standby ................................................................................................................... 19
Asynchronous Commands .......................................................................................................................... 19
Asynchronous Addresses ............................................................................................................................ 21
Asynchronous Data Input ........................................................................................................................... 22
Asynchronous Data Output ......................................................................................................................... 23
Write Protect# ............................................................................................................................................ 24
Ready/Busy# .............................................................................................................................................. 24
Device Initialization ....................................................................................................................................... 29
Power Cycle Requirements .............................................................................................................................. 30
Command Definitions .................................................................................................................................... 31
Reset Operations ............................................................................................................................................ 34
RESET (FFh) ............................................................................................................................................... 34
Identification Operations ................................................................................................................................ 35
READ ID (90h) ............................................................................................................................................ 35
READ ID Parameter Tables .............................................................................................................................. 36
READ PARAMETER PAGE (ECh) ...................................................................................................................... 38
Parameter Page Data Structure Tables ............................................................................................................. 39
READ UNIQUE ID (EDh) ................................................................................................................................ 44
Feature Operations ......................................................................................................................................... 45
SET FEATURES (EFh) .................................................................................................................................. 45
GET FEATURES (EEh) ................................................................................................................................. 46
Status Operations ........................................................................................................................................... 49
READ STATUS (70h) ................................................................................................................................... 49
READ STATUS ENHANCED (78h) ................................................................................................................ 50
Column Address Operations ........................................................................................................................... 51
RANDOM DATA READ (05h-E0h) ................................................................................................................ 51
RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................ 52
RANDOM DATA INPUT (85h) ...................................................................................................................... 53
PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 54
Read Operations ............................................................................................................................................. 56
READ MODE (00h) ..................................................................................................................................... 58
READ PAGE (00h-30h) ................................................................................................................................ 58
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 59
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 60
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 62
READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... 63
Program Operations ....................................................................................................................................... 65
PROGRAM PAGE (80h-10h) ......................................................................................................................... 66
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 66
PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... 69
Erase Operations ............................................................................................................................................ 71
ERASE BLOCK (60h-D0h) ............................................................................................................................ 71
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m71m_8Gb_nand.pdf – Rev. L 1/12 EN
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Micron Confidential and Proprietary
8Gb,16Gb: x8, x16 NAND Flash Memory
Features
ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 72
Internal Data Move Operations ....................................................................................................................... 73
READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 74
PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 75
PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................. 76
Block Lock Feature ......................................................................................................................................... 77
WP# and Block Lock ................................................................................................................................... 77
UNLOCK (23h-24h) .................................................................................................................................... 77
LOCK (2Ah) ................................................................................................................................................ 80
LOCK TIGHT (2Ch) ..................................................................................................................................... 81
BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 82
One-Time Programmable (OTP) Operations .................................................................................................... 84
Legacy OTP Commands .............................................................................................................................. 84
OTP DATA PROGRAM (80h-10h) ................................................................................................................. 85
RANDOM DATA INPUT (85h) ...................................................................................................................... 86
OTP DATA PROTECT (80h-10) ..................................................................................................................... 87
OTP DATA READ (00h-30h) ......................................................................................................................... 89
Two-Plane Operations .................................................................................................................................... 91
Two-Plane Addressing ................................................................................................................................ 91
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 100
Error Management ........................................................................................................................................ 101
Electrical Specifications ................................................................................................................................. 102
Electrical Specifications – DC Characteristics and Operating Conditions .......................................................... 104
Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 106
Electrical Specifications – Program/Erase Characteristics ................................................................................ 109
Asynchronous Interface Timing Diagrams ...................................................................................................... 110
Revision History ............................................................................................................................................ 121
Rev. L, Production – 2/12 ........................................................................................................................... 121
Rev. K, Production – 1/12 ........................................................................................................................... 121
Rev. J, Production – 12/11 .......................................................................................................................... 121
Rev. I, Production – 8/11 ............................................................................................................................ 121
Rev. H, Production – 7/11 ........................................................................................................................... 121
Rev. G, Advance – 3/11 ............................................................................................................................... 121
Rev. F, Advance – 12/10 .............................................................................................................................. 121
Rev. E, Advance – 11/10 .............................................................................................................................. 121
Rev. D, Advance – 10/10 ............................................................................................................................. 121
Rev. C, Advance – 8/10 ............................................................................................................................... 122
Rev. B, Advance – 7/10 ............................................................................................................................... 122
Rev. A, Advance – 3/10 ............................................................................................................................... 122
PDF: 09005aef83ea4f61
m71m_8Gb_nand.pdf – Rev. L 1/12 EN
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Micron Confidential and Proprietary
8Gb,16Gb: x8, x16 NAND Flash Memory
Features
List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) ................................................................................................ 9
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ........................................................................................ 10
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11
Figure 5: 48-Pin TSOP – Type 1, CPL ............................................................................................................... 12
Figure 6: 63-Ball VFBGA ................................................................................................................................ 13
Figure 7: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 14
Figure 8: Array Organization – 8Gb x 8 ............................................................................................................ 15
Figure 9: Array Organization – 8Gb x 16 .......................................................................................................... 16
Figure 10: Array Organization – 16Gb x 8, Dual-Die, Single-CE# Bare Die Configuration ................................... 17
Figure 11: Array Organization – 16Gb x 16, Dual-Die, Single-CE# Bare Die Configuration ................................. 18
Figure 12: Asynchronous Command Latch Cycle ............................................................................................ 20
Figure 13: Asynchronous Address Latch Cycle ................................................................................................ 21
Figure 14: Asynchronous Data Input Cycles .................................................................................................... 22
Figure 15: Asynchronous Data Output Cycles ................................................................................................. 23
Figure 16: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 24
Figure 17: READ/BUSY# Open Drain .............................................................................................................. 25
Figure 18: tFall and tRise (3.3V VCC) ................................................................................................................ 26
Figure 19: tFall and tRise (1.8V VCC) ................................................................................................................ 26
Figure 20: IOL vs. Rp (VCC = 3.3V VCC) .............................................................................................................. 27
Figure 21: IOL vs. Rp (1.8V VCC) ....................................................................................................................... 27
Figure 22: TC vs. Rp ....................................................................................................................................... 28
Figure 23: R/B# Power-On Behavior ............................................................................................................... 29
Figure 24: RESET (FFh) Operation .................................................................................................................. 34
Figure 25: READ ID (90h) with 00h Address Operation .................................................................................... 35
Figure 26: READ ID (90h) with 20h Address Operation .................................................................................... 35
Figure 27: READ PARAMETER (ECh) Operation .............................................................................................. 38
Figure 28: READ UNIQUE ID (EDh) Operation ............................................................................................... 44
Figure 29: SET FEATURES (EFh) Operation .................................................................................................... 46
Figure 30: GET FEATURES (EEh) Operation .................................................................................................... 46
Figure 31: READ STATUS (70h) Operation ...................................................................................................... 50
Figure 32: READ STATUS ENHANCED (78h) Operation ................................................................................... 50
Figure 33: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 51
Figure 34: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 52
Figure 35: RANDOM DATA INPUT (85h) Operation ........................................................................................ 53
Figure 36: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 55
Figure 37: READ PAGE (00h-30h) Operation ................................................................................................... 59
Figure 38: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 60
Figure 39: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 61
Figure 40: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 62
Figure 41: READ PAGE TWO-PLANE (00h-00h-30h) Operation ........................................................................ 64
Figure 42: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 66
Figure 43: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 68
Figure 44: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 68
Figure 45: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ....................................................................... 70
Figure 46: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 71
Figure 47: ERASE BLOCK TWO-PLANE (60h–D1h) Operation .......................................................................... 72
Figure 48: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 74
Figure 49: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ..................... 74
Figure 50: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ........................................................ 75
PDF: 09005aef83ea4f61
m71m_8Gb_nand.pdf – Rev. L 1/12 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.