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NORTECROECMOMMEMNDENEIDDSLER6DE2PF88OL4ARCCN ®EEMWENDTEDSPIaAGtRaNTSSheet
Single-Phase Core Regulator for IMVP-6®
Mobile CPUs
The ISL6261A is a single-phase buck regulator
implementing lntel® IMVP-6® protocol, with embedded gate
drivers. lntel® Mobile Voltage Positioning (IMVP) is a smart
voltage regulation technology effectively reducing power
dissipation in lntel® Pentium processors.
The heart of the ISL6261A is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional multi-phase buck regulator, the R3
Technology™ has faster transient response. This is due to
the R3 modulator commanding variable switching frequency
during a load transient.
The ISL6261A provides three operation modes: the
Continuous Conduction Mode (CCM), the Diode Emulation
Mode (DEM) and the Enhanced Diode Emulation Mode
(EDEM). To boost battery life, the ISL6261A changes its
operation mode based on CPU mode signals DPRSLRVR
and DPRSTP#, and the FDE pin setting, to maximize the
efficiency. In CPU active mode, the ISL6261A commands
the CCM operation. When the CPU enters deeper sleep
mode, the ISL6261A enables the DEM to maximize the
efficiency at light load. Asserting the FDE pin of the
ISL6261A in CPU deeper sleep mode will enable the EDEM
to further decrease the switching frequency at light load and
increase the regulator efficiency.
A 7-bit Digital-to-Analog Converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
The ISL6261A has 0.5% system voltage accuracy over
temperature.
A unity-gain differential amplifier provides remote voltage
sensing at the CPU die. This allows the voltage on the CPU
die to be accurately measured and regulated per lntel®
IMVP-6 specification. Current sensing can be implemented
through either lossless inductor DCR sensing or precise
resistor sensing. If DCR sensing is used, an NTC thermistor
network will thermally compensates the gain and the time
constant variations caused by the inductor DCR change.
The ISL6261A provides the power monitor function through
the PMON pin. PMON output is a high-bandwidth analog
voltage signal representing the CPU instantaneous power.
The power monitor function can be used by the system to
optimize the overall power consumption, extending battery
run time.
November 5, 2009
ISL6261A
FN6354.3
Features
• Precision single-phase CORE voltage regulator
- 0.5% system accuracy over temperature
- Enhanced load line accuracy
• Internal gate driver with 2A driving capability
• Microprocessor voltage identification input
- 7-Bit VID input
- 0.300V to 1.500V in 12.5mV steps
- Support VID change on-the-fly
• Multiple current sensing schemes supported
- Lossless inductor DCR current sensing
- Precision resistive current sensing
• Thermal monitor
• Power monitor indicating CPU instantaneous power
• User programmable switching frequency
• Differential remote voltage sensing at CPU die
• Overvoltage, undervoltage, and overcurrent protection
• Pb-free (RoHS compliant)
Ordering Information
PART NUMBER
PART
(Notes 2, 3)
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-Free) DWG. #
ISL6261ACRZ ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
ISL6261ACRZ-T* ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
(Note 1)
Tape and Reel
ISL6261AIRZ 6261A IRZ -40 to +100 40 Ld 6x6 QFN L40.6x6
ISL6261AIRZ-T* 6261A IRZ
(Note 1)
-40 to +100 40 Ld 6x6 QFN L40.6x6
Tape and Reel
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL6261A. For more information on MSL please see
techbrief TB363.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007, 2009. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.

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Pinout
ISL6261A
ISL6261A
(40 LD QFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
FDE 1
PMON 2
RBIAS 3
VR_TT# 4
NTC 5
SOFT 6
OCSET 7
VW 8
COMP 9
FB 10
GND PAD
(BOTTOM)
30 VID2
29 VID1
28 VID0
27 VCCP
26 LGATE
25 VSSP
24 PHASE
23 UGATE
22 BOOT
21 NC
11 12 13 14 15 16 17 18 19 20
2 FN6354.3
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ISL6261A
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
. . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5) θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
33
6
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V
Ambient Temperature
ISL6261ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL6261AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature
ISL6261ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
ISL6261AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. Boldface limits apply over the operating
temperature range, -40°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNITS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 3.3V
VR_ON = 0V
- 3.1 3.6 mA
- - 1 µA
+3.3V Supply Current
Battery Supply Current at VIN Pin
POR (Power-On Reset) Threshold
SYSTEM AND REFERENCES
I3V3
IVIN
PORr
PORf
No load on CLK_EN# pin
VR_ON = 0, VIN = 25V
VDD rising
VDD falling
-
-
-
3.85
- 1 µA
- 1 µA
4.35 4.5 V
4.1 - V
System Accuracy
%Error
(Vcc_core)
ISL6261ACRZ
No load, close loop, active mode,
TA =-10°C to +100°C, VID = 0.75V to 1.5V
VID = 0.5V to 0.7375V
-0.5
-8
- 0.5 %
- 8 mV
VID = 0.3V to 0.4875V
-15 - 15 mV
%Error
No load, close loop, active mode,
-0.8
- 0.8 %
(Vcc_core)
ISL6261AIRZ
VID = 0.75V to 1.5V
VID = 0.5V to 0.7375V
-10 - 10 mV
VID = 0.3V to 0.4875V
-18 - 18 mV
RBIAS Voltage
Boot Voltage
Maximum Output Voltage
RRBIAS
VBOOT
VCC_CORE
(max)
RRBIAS = 147kΩ
VID = [0000000]
1.45
1.188
-
1.47
1.2
1.5
1.49
1.212
-
V
V
V
Minimum Output Voltage
VCC_CORE
(min)
VID = [1100000]
- 0.3 - V
VID Off State
VID = [1111111]
- 0.0 - V
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW RFSET = 7kΩ, Vcomp = 2V
318 333 348 kHz
3 FN6354.3
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ISL6261A
Electrical Specifications VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued) Boldface limits apply over the
operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNITS
Adjustment Range
200 - 500 kHz
AMPLIFIERS
Droop Amplifier Offset
-0.3 - 0.3 mV
Error Amp DC Gain (Note 6)
Error Amp Gain-Bandwidth Product
(Note 6)
AV0
GBW
CL = 20pF
- 90 - dB
- 18 - MHz
Error Amp Slew Rate (Note 6)
FB Input Current
SOFT-START CURRENT
SR
IIN(FB)
CL = 20pF
- 5.0 - V/µs
- 10 150 nA
Soft-start Current
Soft Geyserville Current
Soft Deeper Sleep Entry Current
Soft Deeper Sleep Exit Current
Soft Deeper Sleep Exit Current
POWER MONITOR
ISS
IGV
IC4
IC4EA
IC4EB
|SOFT - REF|>100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
-47
±180
-46
36
175
-42
±205
-41
41
200
-37
±230
-36
46
225
µA
µA
µA
µA
µA
PMON Output Voltage Range
PMON Maximum Voltage
PMON Sourcing Current
PMON Sinking Current
Maximum Current Sinking Capability
VPMON
VPMONMAX
ISC_PMON
ISK_PMON
VSEN = 1.2V, VDROOP - VO = 40mV
VSEN = 1V, VDROOP - VO = 10mV
VSEN = 1V, VDROOP - VO = 25mV
VSEN = 1V, VDROOP - VO = 25mV
1.638
1.680
0.308
0.350
2.8 3.0
2-
2-
PMON/250Ω PMON/180Ω
1.722
0.392
-
-
-
PMON
/130Ω
V
V
V
mA
mA
A
PMON Impedance
ZPMON
When PMON current is within its
ourcing/sinking current range (Note 6)
-
7 -Ω
GATE DRIVER DRIVING CAPABILITY (Note 6)
UGATE Source Resistance
RSRC(UGATE) 500mA source current
- 1 1.5 Ω
UGATE Source Current
ISRC(UGATE)
VUGATE_PHASE = 2.5V
- 2 -A
UGATE Sink Resistance
RSNK(UGATE) 500mA sink current
- 1 1.5 Ω
UGATE Sink Current
ISNK(UGATE)
VUGATE_PHASE = 2.5V
- 2 -A
LGATE Source Resistance
RSRC(LGATE) 500mA source current
- 1 1.5 Ω
LGATE Source Current
ISRC(LGATE)
VLGATE = 2.5V
- 2 -A
LGATE Sink Resistance
RSNK(LGATE) 500mA sink current
- 0.5 0.9 Ω
LGATE Sink Current
ISNK(LGATE)
VLGATE = 2.5V
- 4 -A
UGATE to PHASE Resistance
RP(UGATE)
- 1.1 - kΩ
GATE DRIVER SWITCHING TIMING (Refer to “Gate Driver Timing Diagram” on page 6)
UGATE Turn-on Propagation Delay
tPDHU
ISL6261ACRZ
tPDHU
ISL6261AIRZ
TA = -10°C to +100°C,
PVCC = 5V, output unloaded
PVCC = 5V, output unloaded
20 30 44 ns
18 30 44 ns
LGATE Turn-on Propagation Delay
tPDHL
ISL6261ACRZ
tPDHL
ISL6261AIRZ
TA = -10°C to +100°C,
PVCC = 5V, output unloaded
PVCC = 5V, output unloaded
7 15 30 ns
5 15 30 ns
BOOTSTRAP DIODE
Forward Voltage
VDDP = 5V, forward bias current = 2mA
0.43
0.58 0.72 V
4 FN6354.3
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ISL6261A
Electrical Specifications VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued) Boldface limits apply over the
operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNITS
Leakage
POWER GOOD and PROTECTION MONITOR
VR = 16V
- - 1 μA
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
VOL
IOH
tpgd
IPGOOD = 4mA
PGOOD = 3.3V
CLK_EN# low to PGOOD high
- 0.11 0.4 V
-1 - 1 µA
5.5 6.8 8.1 ms
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OC Threshold Offset
OVH
OVHS
VO rising above setpoint > 1ms
VO rising above setpoint > 0.5µs
I(RBIAS) = 10µA
DROOP rising above OCSET > 120µs
155
1.675
9.8
-3.5
195 235 mV
1.7
1.725
V
10 10.2 µA
- 3.5 mV
Undervoltage Threshold
(VDIFF-SOFT)
UVf VO below set point for > 1ms
-360
-300
-240 mV
LOGIC THRESHOLDS
VR_ON and DPRSLPVR Input Low
VR_ON and DPRSLPVR Input High
Leakage Current on VR_ON
Leakage Current on DPRSLPVR
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
VIL(3.3V)
VIH(3.3V)
IIL
IIH
IIL_DPRSLP
IIH_DPRSLP
VIL(1.0V)
Logic input is low
Logic input is high
DPRSLPVR logic input is low
DPRSLPVR logic input is high
- - 1V
2.3 - - V
-1 0 - μA
- 0 1 μA
-1 0 - μA
- 0.45 1 μA
- - 0.3 V
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH(1.0V)
0.7 - - V
Leakage Current of DAC(VID0-VID6) IIL DPRSLPVR logic input is low
and DPRSTP#
IIH DPRSLPVR logic input is high
THERMAL MONITOR
-1 0 - μA
- 0.45 1 μA
NTC Source Current
NTC = 1.3 V
53 60 67 µA
Over-temperature Threshold
V(NTC) falling
1.17 1.2 1.25 V
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
RTT I = 20mA
- 5 9Ω
CLK_EN# High Output Voltage
VOH 3V3 = 3.3V, I = -4mA
2.9 3.1 - V
CLK_EN# Low Output Voltage
VOL
ICLK_EN# = 4mA
- 0.18 0.4 V
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5 FN6354.3
November 5, 2009