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®
Data Sheet
ISL6455, ISL6455A
December 21, 2005
FN9196.0
Triple Output Regulator with Single
Synchronous Buck and Dual LDO
The ISL6455 is a highly integrated triple output regulator
which provides a single chip solution for FPGAs and wireless
chipset power management. The device integrates a high
efficiency synchronous buck regulator (adjustable) with two
ultra low noise LDO regulators (adjustable). Either the
ISL6455 or ISL6455A can be selected based on whether
3.3V ±10% or 5V ±10% is required as an input voltage.
The synchronous current mode control PWM regulator with
integrated N- and P-channel power MOSFET provides
adjustable voltages based on external resistor setting.
Synchronous rectification with internal MOSFETs is used to
achieve higher efficiency and reduced number of external
components. Operating frequency is typically 750kHz
allowing the use of smaller inductor and capacitor values.
The device can be synchronized to an external clock signal
in the range of 500kHz to 1MHz. The PG_PWM output
indicates loss of regulation on PWM output.
The ISL6455 also has two LDO adjustable regulators using
internal PMOS transistors as pass devices. LDO2 features
ultra low noise typically below 30µVRMS to aid VCO stability.
The EN_LDO pin controls LDO1 and LDO2 outputs. The
ISL6455 also integrates a RESET function, which eliminates
the need for additional RESET IC required in WLAN and
other applications. The IC asserts a RESET signal whenever
the VIN supply voltage drops below a preset threshold,
keeping it asserted for at least 25ms after VIN has risen
above the reset threshold. The PG_LDO output indicates
loss of regulation on either of the two LDO outputs. Other
features include overcurrent protection and thermal
shutdown for all the three outputs.
High integration and the thin Quad Flat No-lead (QFN)
package makes ISL6455 an ideal choice for powering
FPGAs and small form factor wireless cards such as
PCMCIA, mini-PCI and Cardbus-32.
Ordering Information
PART NUMBER* PART
TEMP. PACKAGE PKG.
(Note)
MARKING RANGE (°C) (Pb-Free) DWG. #
ISL6455IRZ
6455IRZ
-40 to 85 24 Ld QFN L24.4x4B
ISL6455AIRZ 6455AIRZ -40 to 85 24 Ld QFN L24.4x4B
Add “-TK” or T5K suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Fully integrated synchronous buck regulator + dual LDO
• PWM output voltage adjustable.
- 0.8V to 2.5V with ISL6455 (VIN = 3.3V)
- 0.8V to 3.3V with ISL6455A (VIN = 5.0V)
• High output current. . . . . . . . . . . . . . . . . . . . . . . . . 600mA
• Dual LDO adjustable options
- LDO1, 1.2V to Vin-0.3V (3.3Vmax). . . . . . . . . . . 300mA
- LDO2, 1.2V to Vin-0.3V (3.3Vmax). . . . . . . . . . . 300mA
• Ultra-compact DC/DC converter design
• Stable with small ceramic output capacitors and no load
• High conversion efficiency
• Low shutdown supply current
• Low dropout voltage for LDOs
- LDO1 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA
- LDO2 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA
• Low output voltage noise
- <30µVRMS (typical) for LDO2 (VCO supply)
• PG_LDO and PG_PWM (PWM and LDO) outputs
• Extensive circuit protection and monitoring features
- PWM overvoltage protection
- Overcurrent protection
- Shutdown
- Thermal shutdown
• Integrated RESET output for microprocessor reset
• Proven reference design for total WLAN system solution
• QFN package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale package footprint Improves PCB
efficiency and is thinner in Profile
• Pb-free plus anneal available (RoHS compliant)
Applications
• WLAN cards
- PCMCIA, Cardbus32, MiniPCI cards
- Compact flash cards
• Hand-held instruments
Related Literature
• TB363 - Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)
• TB389 - PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinout
ISL6455, ISL6455A
ISL6455, ISL6455A (QFN)
TOP VIEW
24 23 22 21 20 19
SGND 1
FB_LDO2 2
18 GND
17 CT
FB_LDO1 3
16 VOUT
CC1 4
15 RESET
GND_LDO 5
14 EN
VOUT1 6
13 SYNC
7 8 9 10 11 12
Typical Application Schematic
3.3V
Re
Rf
C2 33nF
3.3V
C10
10µF
C8
0.1µF
C9
1.0µF
L1
8.2µH
C7
10µF
R1 10k
1 22 21 20 19 18
FB_PWM
11
16 VOUT
PG_PWM 12
24 EN_LDO
SYNC 13
CC1
4
ISL6455
9 VOUT2
5 GND_LDO
EN
14
R3 PG_LDO 23
6 VOUT1
FB_LDO1
3
10k 15 17 7 8 10 2
C4 10µF
C3
10µF
Rc
Ra
Rb
Rd
Vopwm
Vout2
Vout1
NOTE: All capacitors are ceramic.
C1
10nF
C5
4.7µF
C6
33nF
3.3V
2 FN9196.0
December 21, 2005

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Functional Block Diagram
ISL6455, ISL6455A
10nF
3.3V
10k
CT
RESET
PG_LDO
RESET
POR POR
BAND
GAP
REF
1.2V
WINDOW
COMP.
Gm
EN_LDO
GND_LDO
EN
CONTROL
LOGIC
THERMAL
SHUTDOWN
150°C
Gm
WINDOW
COMP.
VIN
RTN
VIN
SGND
FB_PWM
SOFT-
START
SLOPE
COMPENSATION
EA GM
EN
PWM
OVERCURRENT,
OVERVOLTAGE
LOGIC
COMPENSATION
CURRENT
SENSE
GATE
DRIVE
3.3V
750kHz
OSCILLATOR
EN
POWER GOOD
PWM
VOUT
UVLO
SYNC EN
10k 10k
PWM
REFERENCE
0.45V
3.3V
10k
PG_PWM
+-
LDO1
+-
LDO2
VIN_LDO
VIN_LDO
VIN_LDO
VOUT1
VOUT1
FB_LDO1
Rc
Rd
0
10µF
CC1
CC2
33nF
33nF
VOUT2
VOUT2
FB_LDO2
Ra
0
10µF
PVCC
3.3V
Rb
8.2µH
LX VOUT
10µF
PGND
Re
GND
Rf
VOUT
3 FN9196.0
December 21, 2005

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ISL6455, ISL6455A
Absolute Maximum Ratings (Note 1)
Supply Voltage VIN, PVCC, VIN_LDO. . . . . . . . GND -0.3V to +6.0V
Max Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . 600mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
24 Ld QFN (Note 1) . . . . . . . . . . . . . . .
42
6
Maximum Junction Temperature (Plastic Package) . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V for ISL6455 and
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = -40°C to 85° (Note 2), typical
values are at TA = 25°C.
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY
VIN_PWM Supply Voltage Range
ISL6455
3.0 3.3 3.6
V
ISL6455A
4.2 5.0 5.5
V
VIN_LDO Supply Voltage Range
3.0 - 5.5 V
Operating Supply Current (Note 3) for ISL6455
Operating Supply Current (Note 3) for ISL6455A
Shutdown Supply Current
ISL6455 and ISL6455A
VIN = VIN_LDO = PVCC = 3.3V
fSW = 750kHz, COUT = 10µF, IL = 0mA
VIN = VIN_LDO = PVCC = 5.0V
fSW = 750kHz, COUT = 10µF, IL = 0mA
EN = EN_LDO = GND
- 2.5 3.1 mA
- 3.5 4.5 mA
- 5 10 µA
Input Bias Current (EN pin)
VIN_PWM UVLO Threshold for ISL6455
VIN_PWM UVLO Threshold for ISL6455A
VIN_LDO UVLO Threshold for ISL6455 and
ISL6455A
Thermal Shutdown Temperature (Note 6)
EN = EN_LDO = GND/VIN
VTR
VTF
VTR
VTF
VTR
VTF
Rising Threshold
-1.5 1.0 1.5
2.55 2.65 2.71
2.51 2.56 2.61
3.94 4.05 4.13
3.78 3.89 3.97
2.46 2.64 2.82
2.53 2.59 2.66
- 150 -
µA
V
V
V
V
V
V
°C
Thermal Shutdown Hysteresis (Note 6)
- 20 - °C
SYNCHRONOUS BUCK PWM REGULATOR
Output Voltage
ISL6455
0.8 - 2.5 V
ISL6455A
0.8 - 3.3 V
FB_PWM Initial Voltage Accuracy (Note 7)
FB_PWM Line Regulation
VREF = 0.45V, IOUT = 3mA, TA = -40°C to 85°C
IO = 3mA, VIN = PVCC = 3.0-3.6V (ISL6455)
or 4.2-5.5V (6455A)
-0.9 - 0.9 %
-0.5 - 0.5 %
FB_PWM Load Regulation
IO = 3mA to 500mA, VIN = PVCC = 3.0-3.6V (ISL6455) -1.1 - +1.1 %
or 4.2-5.5V (ISL6455A)
Peak Output Current Limit
700mA
-
1300
mA
PMOS rDS(ON)
NMOS rDS(ON)
IOUT = 200mA
IOUT = 200mA
- 170 - m
- 50 - m
4 FN9196.0
December 21, 2005

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ISL6455, ISL6455A
Electrical Specifications
PARAMETER
Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V for ISL6455 and
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = -40°C to 85° (Note 2), typical
values are at TA = 25°C. (Continued)
TEST CONDITIONS
MIN TYP MAX UNITS
Efficiency
Soft-Start Time
IOUT = 200mA, VIN = 3.3V, VOUT = 1.8V
4096 Clock Cycles @ 750kHz
- 93 - %
- 5.5 - ms
OSCILLATOR
Oscillator Frequency
TA = -40°C to +85°C
Frequency Synchronization Range (fSYNC)
Clock signal on SYNC pin
SYNC High Level Input Voltage
As % of VIN
SYNC Low Level Input Voltage
As % of VIN
Sync Input Leakage Current
SYNC = GND or VIN
Min Duty Cycle of External Clock Signal (Note 6)
620 750 880 kHz
500 - 1000 kHz
70 -
-%
- - 30 %
-1.0 - 1.0 µA
- 20 - %
Max Duty Cycle of External Clock Signal (Note 6)
- 80 - %
PG_PWM
Rising Threshold
Falling Threshold
Leakage Current
LDO1 SPECIFICATIONS
1.2mA source/sink, FB_PWM vs 0.45V VREF
FB_PWM vs 0.45V VREF
PG_PWM = GND or VIN
+5.5
-10.5
-
8.0
-8.0
0.01
+10.5
-5.5
0.1
%
%
µA
Output Voltage Range
VIN_VLDO > 3.0V
1.2 - 2.7 V
Output Voltage Range
VIN_VLDO > 3.6V
1.2 - 3.3 V
FB_LDO1 Voltage Accuracy (Note 7)
Maximum Output Current (Note 6)
Output Current Limit (Note 6)
IOUT = 10mA
VIN = 3.6V
-1.5 - 1.5 %
300 -
- mA
350 420 600 mA
Dropout Voltage (Note 4)
FB_LDO1 Line Regulation
FB_LDO1 Load Regulation
Output Voltage Noise (Note 6)
LDO2 SPECIFICATIONS
IOUT = 300mA
IOUT = 10mA, VIN_LDO = 3.0-5.5V
IOUT = 10mA to 300mA
10Hz < f < 100kHz, IOUT = 10mA
COUT = 2.2µF
COUT = 10µF
- 150 300 mV
-0.5 - 0.5 %/V
-0.5 - 0.5 %
- 65 - µVRMS
- 60 - µVRMS
Output Voltage Range
VIN_VLDO > 3.0V
1.2 - 2.7 V
Output Voltage Range
VIN_VLDO > 3.6V
1.2 - 3.3 V
FB_LDO2 Voltage Accuracy (Note 7)
Maximum Output Current (Note 6)
Output Current Limit (Note 6)
IOUT = 10mA
VIN = 3.6V
-1.5 - 1.5 %
300 -
- mA
350 420 600 mA
Dropout Voltage (Note 4)
FB_LDO2 Line Regulation
FB_LDO2 Load Regulation
Output Voltage Noise (Note 6)
IOUT = 300mA
IOUT = 10mA, VIN_LDO = 3.0-5.5V
IOUT = 10mA to 300mA
10Hz < f < 100kHz, IOUT = 10mA
COUT = 2.2µF
COUT = 10µF
- 150 300 mV
-0.5 - 0.5 %/V
-0.5 - 0.5 %
- 30 - µVRMS
- 20 - µVRMS
5 FN9196.0
December 21, 2005