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Freescale Semiconductor
Data Sheet: Technical Data
P3041 QorIQ
Integrated Processor
Hardware Specifications
Document Number: P3041EC
Rev. 2, 02/2013
P3041
FC-PBGA–1295
37.5 mm x 37.5 mm
The P3041 QorIQ integrated processor utilizes four processor
cores built on Power Architecture® technology. The cores
include high-performance data path acceleration logic and
network and peripheral bus interfaces required for
networking, telecom/datacom, wireless infrastructure, and
aerospace applications.
This chip can be used for combined control, data path, and
application layer processing in routers, switches, base station
controllers, and general-purpose embedded computing. Its
high level of integration offers significant performance
benefits compared to multiple discrete devices while also
greatly simplifying board design.
The chip includes the following functions and features:
• Four e500mc Power Architecture cores, each with a
backside 128 KB L2 cache with ECC
– Three levels of instructions: User, supervisor, and
hypervisor
– Independent boot and reset
– Secure boot capability
• CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet end-points
• CoreNet platform cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os,
datapath accelerators, and high and low speed peripheral
interfaces
• One 10-Gigabit Ethernet (XAUI) controller
• Five 1-Gigabit Ethernet controllers
– SGMII interfaces
— 2.5 Gbps SGMII interfaces
– RGMII interfaces
• One 64-bit DDR3 SDRAM memory controller with ECC
• Multicore programmable interrupt controller
• Four I2C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller (eLBC)
• Four PCI Express 2.0 controllers/ports
• Two serial RapidIO® controllers/ports (sRIO port)
supporting version 1.3 with features from 2.1
• Two serial ATA (SATA 2.0) controllers
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interfaces (eSPI)
• 2× high-speed USB 2.0 controllers with integrated PHYs
© 2010–2013 Freescale Semiconductor, Inc. All rights reserved.

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Table of Contents
1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3
1.1 1295 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . .3
1.2 Pinout List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .51
2.2 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3 Power-Down Requirements . . . . . . . . . . . . . . . . . . . . .58
2.4 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.5 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.6 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.7 Power-On Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.8 DDR3 and DDR3L SDRAM Controller . . . . . . . . . . . . .66
2.9 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
2.11 Ethernet: Datapath Three-Speed Ethernet (dTSEC),
Management Interface, IEEE Std 1588. . . . . . . . . . . . .78
2.12 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
2.13 Enhanced Local Bus Interface (eLBC) . . . . . . . . . . . . .87
2.14 Enhanced Secure Digital Host Controller (eSDHC) . . .91
2.15 Multicore Programmable Interrupt Controller (MPIC) and
Trust Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
2.16 JTAG Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
2.17 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.19 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 100
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 132
3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
3.2 Supply Power Default Setting . . . . . . . . . . . . . . . . . . 139
3.3 Power Supply Design . . . . . . . . . . . . . . . . . . . . . . . . 141
3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 143
3.5 SerDes Block Power Supply Decoupling
Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 143
3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 143
3.7 Recommended Thermal Model . . . . . . . . . . . . . . . . . 152
3.8 Thermal Management Information . . . . . . . . . . . . . . 153
4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 154
4.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 155
5 Security Fuse Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.1 Part Numbering Nomenclature . . . . . . . . . . . . . . . . . 156
6.2 Orderable Part Numbers Addressed by this Document157
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2
2 Freescale Semiconductor

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This figure shows the major functional units within the chip.
Pin Assignments and Reset States
eOpenPIC
PreBoot
Loader
Security
Monitor
Internal
BootROM
Power Mgmt
SD/MMC
SPI
2x DUART
4x I2C
2x
USB 2.0 PHY
Clocks/Reset
GPIO
CCSR
P3041
128-Kbyte
Backside
L2 Cache
Power Architecture®
e500mc Core
32-Kbyte 32-Kbyte
D-Cache I-Cache
1024-Kbyte
Frontside
CoreNet Platform
Cache
64-bit
DDR3/3L
Memory Controller
PAMU PAMU
PAMU
CoreNet
Coherency Fabric
PAMU
Peripheral
Access Mgmt Unit
PAMU
eLBC
Security
4.2
Queue
Mgr
RapidIO
RMan
Pattern
Match
Engine
2.1
Buffer
Mgr
Frame Manager
Parse, Classify,
Distribute
Buffer
1GE 1GE
10GE
1GE
1GE
1GE
2x DMA
18-Lane 5-GHz SerDes
Real Time Debug
Watchpoint
Cross
Trigger
Perf CoreNet
Monitor Trace
Aurora
Figure 1. Block Diagram
1 Pin Assignments and Reset States
This section contains top view and detailed quadrant views of the FC-PBGA ball map diagram followed by a pinout list.
1.1 1295 FC-PBGA Ball Layout Diagrams
These figures show the FC-PBGA ball map diagrams.
P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
3

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Pin Assignments and Reset States
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
A
RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV MDQ MDQ
[A2] [A3] [A4] [A5] [A6] [A7] [A8] [A9] [A10] [A11] [A12] [A13] [3]
[6]
B
RSRV
[B1]
GVDD
[1]
RSRV
[B3]
RSRV
[B4]
GND
[2]
RSRV RSRV GVDD RSRV RSRV
[B6] [B7] [2] [B9] [B10]
GND
[7]
RSRV RSRV GVDD MDQ
[B12] [B13] [3]
[7]
MDM MDQ
[0] [0]
MDQS MDQ
[0] [5]
GND
[24]
GND
[31]
AVDD_
DDR
MVREF
AVDD_
CC
[1]
GND
[16]
RSRV
[A21]
TEMP_
CATH-
ODE
GND
[21]
GND
[17]
LALE
LWE
[1]
RSRV
[A25]
LCS BVDD LGPL
[5] [1] [0]
GND NC SGND SD_RX SVDD SD_RX SGND AVDD_ SVDD
[23] [A27] [1] [1] [1] [3] [2] SRDS1 [2]
NC SD_IMP_ SVDD SD_RX SGND SD_RX SVDD AGND_ SGND
[B26] CAL_RX [9]
[1] [10] [3] [10] SRDS1 [11]
SD_
REF_
CLK1
SD_
REF_
CLK1
SGND
[3]
SVDD
[11]
A
B
C
RSRV
[C1]
RSRV
[C2]
GND
[1]
RSRV RSRV GVDD RSRV MDQ
[C4] [C5] [6] [C7] [16]
GND
[6]
MDQ
[21]
MDQ GVDD RSRV MDQ
[20] [5] [C13] [2]
GND MDQS MDQ GVDD NC
[14] [0] [4] [4] [C19]
NC
[C20]
TEMP_
ANODE
LBCTL
LCLK
[1]
LCLK LGPL
[0] [4]
NC
[C26]
NC
[C27]
SD_RX SGND SD_RX SVDD
[0] [12] [2] [12]
RSRV
[C32]
SGND
[13]
SVDD
[13]
SVDD
[14]
SD_RX
[4]
C
D
RSRV RSRV RSRV GVDD RSRV
[D1] [D2] [D3] [7] [D5]
RSRV
[D6]
GND
[5]
MDQS MDQS GVDD
[2] [2] [8]
MDM
[2]
MDQ
[17]
GND
[13]
MDM
[1]
MDQ GVDD MDQ
[8] [9] [1]
NC
[D18]
LCS
[0]
LCS
[1]
LCS
[3]
LCS
[4]
LAD
[9]
LWE
[0]
LGPL
[2]
LAD
[27]
NC
[D27]
SD_RX SVDD SD_RX SGND
[0] [15] [2] [14]
RSRV
[D32]
XGND
[9]
SD_TX
[4]
SGND
[15]
SD_RX
[4]
D
E
RSRV
[E1]
GVDD
[12]
RSRV
[E3]
RSRV
[E4]
GND
[4]
MDQ
[22]
MDQ GVDD MDQ
[23] [11] [18]
MDQ
[19]
GND
[12]
MDQ
[10]
MDQ GVDD MDQ
[14] [10] [13]
NC
[E16]
GND
[25]
LA
[28]
GND LCS
[18] [2]
LAD
[21]
BVDD
[6]
LAD
[8]
BVDD LGPL
[5] [1]
LGPL
[5]
NC
[E27]
XGND SD_TX
[10] [1]
XGND SD_TX
[11] [3]
XVDD
[8]
XVDD
[9]
SD_TX SGND
[4] [16]
SVDD
[16]
E
F
RSRV
[F1]
RSRV
[F2]
GND
[3]
RSRV
[F4]
RSRV GVDD
[F5] [13]
MDQ
[24]
MDQ
[29]
GND
[11]
MDQ
[28]
MDQ GVDD MDQ MDQS GND
[25] [14] [15] [1] [36]
MDQ
[12]
LAD
[31]
LA
[29]
LAD BVDD LAD
[12] [3] [22]
LAD GND LCS
[19] [26]
[6]
LAD
[4]
BVDD
[4]
GND
[28]
XVDD
[10]
SD_TX
[1]
XVDD
[11]
SD_TX
[3]
XGND
[12]
SD_TX
[5]
SVDD
[17]
SD_RX SD_RX
[5] [5]
F
G
RSRV
[G1]
RSRV
[G2]
RSRV
[G3]
GVDD
[16]
RSRV
[G5]
RSRV
[G6]
GND
[10]
MDQS MDQS GVDD MDM
[3] [3] [17] [3]
MDQ
[11]
GND MDQS MDQ
[35] [1] [9]
GVDD
[18]
GND
[231]
LA
[31]
LAD
[28]
LAD
[25]
GND
[29]
LAD
[11]
LAD
[7]
LAD
[6]
LAD
[17]
LCS
[7]
NC
[G27]
SD_TX
[0]
XGND SD_TX XGND
[13] [2] [14]
XVDD
[12]
SD_TX
[5]
SGND
[17]
SVDD
[18]
SGND
[18]
G
H
RSRV
[H1]
GVDD
[21]
RSRV
[H3]
RSRV
[H4]
GND
[9]
RSRV
[H6]
MDQ
[30]
GVDD
[20]
MDQ
[31]
MDQ
[26]
GND NC
NC GVDD NC
[37] [H12] [H13] [19] [H15]
LDP
[3]
LDP BVDD LAD BVDD LAD
[2] [9] [29] [8] [23]
LAD
[20]
LAD
[18]
LAD
[5]
LAD
[3]
LGPL
[3]
NC
[H27]
SD_TX XGND SD_TX XVDD XGND
[0] [15] [2] [13] [16]
XVDD
[14]
XGND
[17]
SD_RX
[6]
SD_RX
[6]
H
J
RSRV
[J1]
RSRV
[J2]
GND
[8]
RSRV MECC GVDD MECC MECC GND
[J4] [1] [22] [5]
[4] [38]
MDQ
[27]
NC
[J11]
GVDD NC
[25] [J13]
NC
[J14]
LAD
[30]
LWE
[2]
LAD
[15]
LAD
[13]
LAD
[30]
LAD
[26]
GND
[33]
LAD
[10]
GND
[20]
LDP
[0]
LAD
[16]
LAD
[2]
GND
[27]
XVDD
[15]
XGND
[18]
XVDD
[16]
XGND
[19]
XVDD
[17]
SD_TX SD_TX SGND
[6] [6] [19]
SVDD
[19]
J
SEE DETAIL A SEE DETAIL BK
RSRV
[K1]
RSRV
[K2]
RSRV
[K3]
GVDD MDQS MDQS
[24] [8]
[8]
GND
[39]
MDM MECC GVDD NC
[8] [0] [23] [K11]
NC NC
[K12] [K13]
NC
[K14]
LWE SENSE- SENSE- LAD
[3] VDD_CA GND_CA [14]
_PL _PL
GND
[15]
LAD
[27]
LAD BVDD LDP BVDD GND
[24] [2] [1] [7] [30]
LAD
[0]
RSRV
[K27]
XGND
[20]
XGND
[21]
XVDD SD_TX SD_TX
[18] [7]
[7]
SGND
[20]
SVDD
[20]
SD_RX
[7]
SD_RX
[7]
K
L
RSRV GVDD
[L1] [25]
RSRV
[L3]
RSRV
[L4]
GND
[40]
MA
[15]
MECC
[6]
GVDD
[26]
MECC
[7]
MECC VDD
[2] _CA_PL
[1]
GND
[230]
VDD
_CA_PL
[2]
GND
[141]
VDD
_CA_PL
[3]
GND
[98]
VDD
_CA_PL
[4]
GND
[32]
VDD
_CA_PL
[5]
GND
[22]
VDD
_CA_PL
[6]
GND VDD GND VDD
[19] _CA_PL [209] _CA_PL
[7] [8]
LAD
[1]
RSRV
[L27]
RSRV
[L28]
XGND
[22]
XVDD
[19]
XVDD
[20]
XGND SD_RX SD_RX SVDD
[23] [8]
[8] [21]
SGND
[21]
L
M
RSRV
[M1]
RSRV
[M2]
GND
[41]
RSRV RSRV GVDD
[M4] [M5] [27]
MA
[14]
MBA
[2]
GND
[45]
MECC
[3]
GND
[113]
VDD
_CA_PL
[9]
GND
[127]
VDD
_CA_PL
[10]
GND
[142]
VDD
_CA_PL
[11]
GND
[157]
VDD
_CA_PL
[12]
GND VDD
[178] _CA_PL
[13]
GND VDD
[193] _CA_PL
[14]
GND VDD
[208] _CA_PL
[15]
GND VDD
[225] _CA_PL
[16]
GND
[34]
RSRV
[M28]
XVDD
[21]
XGND SD_TX SD_TX
[24] [8]
[8]
SVDD
[22]
SGND
[22]
SD_RX
[9]
SD_RX
[9]
M
N
RSRV
[N1]
RSRV
[N2]
RSRV
[N3]
GVDD
[28]
RSRV
[N5]
MA
[12]
GND MAPAR_ MCKE
[44] ERR [3]
GVDD
[29]
VDD
_CA_PL
[17]
GND
[126]
VDD
_CA_PL
GND
[N14]
VDD
_CA_PL
[19] [19]
GND
[156]
VDD
_CA_PL
GND
160]
VDD
_CA_PL
[20] [21]
GND
[179]
VDD
_CA_PL
[22]
GND
[200]
VDD
_CA_PL
[23]
GND
[210]
VDD
_CA_PL
[24]
GND
[112]
VDD
_CA_PL
[25]
RSRV
[N28]
XGND
[25]
XGND
[26]
XVDD
[22]
XGND SD_TX SD_TX SGND
[27] [9]
[9] [23]
SVDD
[23]
N
P
RSRV
[P1]
GVDD
[31]
RSRV
[P3]
RSRV
[P4]
GND
[43]
MA
[9]
MA
[11]
GVDD MCKE MCKE
[30] [2]
[0]
GND
[113]
VDD
_CA_PL
[26]
GND
[128]
VDD
_CA_PL
[27]
GND
[P15]
VDD
_CA_PL
[28]
GND
[P17]
VDD
_CA_PL
[29]
GND
[177]
VDD
_CA_PL
[30]
GND
[192]
VDD
_CA_PL
[31]
GND
[207]
VDD
_CA_PL
[32]
GND
[224]
VDD
_CA_PL
[33]
GND
[221]
RSRV
[P28]
XGND
[28]
XVDD SD_TX SD_TX
[23] [10] [10]
XVDD
[24]
XGND
[29]
SD_RX
[10]
SD_RX
[10]
P
R
RSRV
[R1]
RSRV
[R2]
GND
[42]
RSRV RSRV GVDD
[R4] [R5] [32]
MA
[8]
MA
[7]
GND
[47]
MCKE
[1]
VDD
_CA_PL
[34]
GND
[125]
VDD
_CA_PL
[35]
GND
[139]
VDD
_CA_PL
[36]
GND
[155]
VDD
_CA_PL
[37]
GND
[161]
VDD
_CA_PL
[38]
GND
[180]
VDD
_CA_PL
[39]
GND VDD
[199] _CA_PL
[40]
GND
[211]
VDD
_CA_PL
[41]
GND
[111]
VDD
_CA_PL
[42]
NC
[R28]
XVDD XGND XVDD XGND SGND
[25] [30] [26] [31] [24]
SVDD
[24]
SVDD
[25]
SGND
[25]
R
T
RSRV
[T1]
RSRV
[T2]
RSRV GVDD RSRV MDIC
[T3] [34] [T5] [0]
GND
[48]
MA
[5]
MA
[6]
GVDD
[33]
GND
[115]
VDD
_CA_PL
[43]
GND
[129]
VDD
_CA_PL
[44]
GND
[144]
VDD
_CA_PL
[45]
GND
[159]
VDD
_CA_PL
[46]
GND VDD
[176] _CA_PL
[47]
GND
[191]
VDD
_CA_PL
[48]
GND
[206]
VDD
_CA_PL
[49]
GND
[223]
VDD
_CA_PL
[50]
GND
[226]
NC
[T28]
XVDD
[27]
SD_TX SD_TX
[11] [11]
XVDD
[28]
SD_RX SD_RX
[11] [11]
SGND
[26]
AGND_
SRDS2
T
U
RSRV GVDD
[U1] [36]
GND
[50]
RSRV
[U4]
GND
[49]
MA
[1]
MA GVDD MA
[2] [37] [3]
MA
[4]
VDD
_CA_PL
[51]
GND
[124]
VDD
_CA_PL
[52]
GND
[138]
VDD
_CA_PL
[53]
GND
[154]
VDD
_CA_PL
[54]
GND
[162]
VDD
_CA_PL
[55]
GND
[181]
VDD
_CA_PL
[56]
GND
[198]
VDD
_CA_PL
[57]
GND
[212]
VDD
_CA_PL
[58]
GND
[110]
VDD
_CA_PL
[59]
NC
[U28]
XGND XVDD XGND
[32] [29] [33]
RSVD
[U32]
SVDD
[26]
SGND
[27]
RSVD
[U35]
AVDD_
SRDS2
U
V
RSRV RSRV
[V1] [V2]
RSRV RSRV
[V3] [V4]
MCK
[1]
MCK GVDD MCK
[1] [38] [2]
MCK
[2]
GND
[54]
GND
VDD
_CA_PL
[116] [60]
GND
[130]
VDD
_CA_PL
[61]
GND
[145]
VDD
_CA_PL
[62]
GND
[222]
VDD
_CA_PL
[63]
GND
[175]
VDD
_CA_PL
[64]
GND
[190]
VDD
_CA_PL
[65]
GND
[205]
VDD
_CA_PL
[66]
GND
[46]
VDD
_CA_PL
[67]
GND
[227]
NC
[V28]
XGND XVDD XGND XVDD
[34] [30] [35] [31]
SD_
REF_
CLK2
SD_
REF_
CLK2
SVDD
[27]
SGND
[28]
V
W
RSRV
[W1]
RSRV
[W2]
RSRV
[W3]
RSRV
[W4]
MCK
[0]
MCK
[0]
GND
[53]
MCK
[3]
MCK
[3]
GVDD
[40]
VDD
_CA_PL
[68]
GND
[123]
VDD
_CA_PL
[69]
GND VDD_CB
[137] [1]
GND
[150]
VDD_CB GND VDD_CB GND
[12] [167] [2] [185]
VDD
_CA_PL
[70]
GND
[197]
VDD
_CA_PL
[71]
GND
[213]
VDD
_CA_PL
[72]
GND
[109]
NC_
W27_
DET
VDD
_CA_PL
[1]
XVDD
[32]
XGND SD_TX SD_TX
[36] [12] [12]
SGND
[29]
SVDD
[28]
SD_RX
[12]
SD_RX
[12]
W
Y
RSRV GVDD
[Y1] [43]
GND
[51]
RSRV GND
[Y4] [52]
RSRV MAPAR_ GVDD
[Y6] OUT [44]
MA
[0]
MBA
[1]
GND
[117]
VDD
_CA_PL
[73]
GND
[131]
VDD
_CA_PL
[74]
GND VDD_CB GND VDD_CB GND VDD_CB
[146] [7] [163] [13] [174] [4]
GND
[189]
VDD
_CA_PL
[75]
GND
[204]
VDD
_CA_PL
[76]
GND
[220]
VDD
_CA_PL
[77]
GND
[228]
NC
[Y28]
SD_TX SD_TX XVDD
[13] [13] [33]
XGND SD_RX SD_RX SGND
[37] [13] [13] [30]
SVDD
[29]
Y
AA
RSRV
[AA1]
RSRV RSRV
[AA2] [AA3]
RSRV
[AA4]
MDIC
[1]
GVDD
[41]
MA
[10]
MBA
[0]
GND
[55]
VDD
MRAS _CA_PL
[78]
GND
[122]
VDD
_CA_PL
[79]
GND VDD_CB GND VDD_CB GND VDD_CB GND VDD_CB GND
[136] [8] [152] [10] [169] [3] [183] [6] [196]
VDD
_CA_PL
[80]
GND
[214]
VDD
_CA_PL
[81]
GND
[108]
VDD
_CA_PL
[82]
NC
[AA28]
XVDD
[1]
XGND SD_TX SD_TX SVDD
[1] [14] [14] [3]
SGND
[4]
SD_RX
[14]
SD_RX
[14]
AA
AB
RSRV
[AB1]
RSRV
[AB2]
RSRV
[AB3]
GVDD
[51]
MDQ
[36]
MDQ
[37]
GND
[56]
MWE
MCS
[2]
GVDD
[52]
GND
[118]
VDD
_CA_PL
[83]
GND
[132]
VDD_CB GND VDD_CB GND VDD_CB GND VDD_CB
[5] [147] [15] [164] [14] [173] [17]
GND
[188]
VDD
_CA_PL
[84]
GND
[203]
VDD
_CA_PL
[85]
GND
[219]
VDD
_CA_PL
[86]
GND
[87]
NC NC
[AB28] [AB29]
XVDD
[2]
XVDD
[3]
XGND SD_TX SD_TX SVDD
[2] [15] [15] [4]
SGND
[5]
AB
AC
RSRV
[AC1]
GVDD
[45]
RSRV
[AC3]
RSRV
[AC4]
GND
[57]
MDQ
[33]
MDQ
[32]
GVDD
[53]
MCS
[0]
VDD
MCAS _CA_PL
[87]
GND
[121]
VDD
_CA_PL
[88]
GND VDD_CB
[135] [9]
GND
[151]
VDD_CB GND VDD_CB GND
[11] [168] [16] [184]
VDD
_CA_PL
[89]
GND
[195]
VDD
_CA_PL
[90]
GND
[215]
VDD
_CA_PL
[91]
GND VDD NC_
[107] _CA_PL AC28
[92]
NC XGND
[AC29] [3]
SD_
REF_
CLK3
SD_
REF_
CLK3
XVDD
[4]
XGND
[4]
SD_RX
[15]
SD_RX
[15]
AC
AD
RSRV
[AD1]
RSRV
[AD2]
GND
[58]
MDQS MDQS GVDD
[4] [4] [46]
MDM
[4]
MODT
[2]
GND
[59]
MODT
[0]
GND
[119]
VDD
_CA_PL
[93]
GND
[133]
VDD
_CA_PL
[94]
GND
[148]
VDD
_CA_PL
[95]
GND
[165]
VDD
_CA_PL
[96]
GND
[172]
VDD
_CA_PL
[97]
GND
[187]
VDD
_CA_PL
[98]
GND
[202]
VDD
_CA_PL
[99]
GND
[218]
VDD
_CA_PL
[100]
GND
[229]
VDD_
LP
NC
[AD29]
XGND
[5]
XGND
[6]
XVDD
[5]
RSVR
[AD33]
RSVR
[AD34]
SGND
[6]
SVDD
[5]
AD
AE
RSRV
[AE1]
RSRV
[AE2]
RSRV GVDD
[AE3] [48]
MDQ
[38]
MDQ
[39]
GND
[60]
MA
[13]
MCS
[1]
GVDD
[47]
VDD
_CA_PL
[101]
GND
[120]
VDD
_CA_PL
[102]
GND
[134]
VDD
_CA_PL
[103]
GND
[153]
VDD
_CA_PL
[104]
GND
[170]
VDD
_CA_PL
GND
[182]
[105]
VDD
_CA_PL
[106]
GND
[194]
VDD
_CA_PL
[107]
GND VDD
[216] _CA_PL
[108]
GND
[106]
GND LP_TMP NC
[97] _DETECT [AE29]
XVDD
[6]
SD_TX SD_TX
[16] [16]
SVDD
[6]
SGND
[7]
AVDD_
SRDS3
AGND_
SRDS3
AE
AF
RSRV
[AF1]
GVDD
[49]
RSRV
[AF3]
RSRV
[AF4]
GND
[61]
MDQ
[34]
MDQ
[35]
GVDD
[50]
MCS
[3]
MODT RSRV RSRV
[3] [AF11] [AF12]
GND
[85]
VDD
_CA_PL
[109]
GND
[149]
VDD
_CA_PL
[110]
GND
[166]
VDD
_CA_PL
[111]
GND
[171]
VDD
_CA_PL
[112]
GND
[186]
VDD
_CA_PL
[113]
GND
[201]
VDD
_CA_PL
GND
[217]
[114]
NC
[AF26]
NC
[AF27]
NC
[AF28]
NC SD_IMP_ XVDD
[AF29] CAL_TX [7]
XGND
[7]
SD_RX SD_RX SVDD
[16] [16] [7]
SGND
[8]
AF
SEE DETAIL CAG
RSRV
[AG1]
RSRV
[AG2]
GND
[62]
RSRV MDQ GVDD MDQ
[AG4] [40] [54] [45]
MDQ
[44]
GND
[63]
RSRV_ RSRV_
MODT AG12 AG12
[1]
IRQ
[8]
AH
RSRV
[AH1]
RSRV
[AH2]
RSRV GVDD
[AH3] [56]
MDQS MDQS
[5] [5]
GND
[64]
MDM
[5]
MDQ
[41]
GVDD
[55]
RSRV
AH11
RSRV_
AH12
GND
[72]
IIC4_ SENSE- SENSE- IRQ
SCL VDD_CB GND_CB [6]
SEE DETAIL DGND
[79]
DMA2_
DACK
GPIO
[7]
OVDD SDHC SDHC CVDD RSRV NC NC NC NC XGND SD_TX SD_TX SGND
[7] _DAT[3] _CMD [3] [AG25] [AG26] [AG27] [AG28] [AG29] [8]
[17] [17]
[9]
SVDD
[8]
SD_RX
[17]
SD_RX
[17]
AG
[0]
IRQ IIC1_ IRQ
[10] SCL [1]
IRQ
[4]
IO_
MSRCID VSEL MSRCID GPIO
[2] [4] [0] [4]
GND
[89]
UART2_ USB1_
CTS AGND
USB1_
VDD_
1P0
USB2_
VDD_
1P0
UTSMBS2_
AGND
SPI_
MISO
RSRV NC XGND
[AH29] [AH30] [38]
XVDD
[34]
SGND
[32]
GND
[102]
SGND
[31]
SVDD
[30]
AH
AJ
RSRV
[AJ1]
GVDD
[57]
RSRV
[AJ3]
RSRV
[AJ4]
GND
[65]
MDQ
[46]
MDQ GVDD MDQ
[47] [58] [42]
MDQ
[43]
GND
[71]
OVDD
[5]
IRQ
[5]
OVDD
[2]
IRQ
[3]
IRQ
[0]
EVT
[0]
OVDD
[3]
MSRCID
[1]
DMA2_
DREQ
[0]
GPIO
[5]
UART2_ OVDD
SOUT [10]
USB1_
AGND
USB1_
VDD_
3P3
USB2_
VDD_
3P3
USB2_
VDD_
3P3
SPI_CS
[1]
CVDD
[1]
EMI2_ EC_XTRNL GND
MDIO _TX_STMP [100]
[2]
EMI1_
MDC
TSEC_
1588_PULSE
_OUT[2]
LVDD
[5]
TSEC_
1588_ALARM
_OUT[1]
AJ
AK
RSRV
[AK1]
RSRV
[AK2]
GND
[66]
RSRV RSRV GVDD MDQ
[AK4] [AK5] [60] [53]
MDQ
[52]
GND
[70]
GVDD
[39]
IRQ
[9]
IRQ
[2]
IIC3_ IRQ_ GND
SCL OUT [78]
EVT
[3]
EVT
[1]
IO_
VSEL
[2]
GND
[84]
CLK_
OUT
GPIO
[6]
GPIO
[1]
UART2_ USB1_
RTS UID
USB1_
VBUS_
CLMP
USB2_ USB2_
VBUS_ UID
CLMP
GND
[96]
SPI_
CLK
EMI2_ EC_XTRNL EC_XTRNL LVDD
MDC _RX_STMP_RX_STMP [1]
[2] [1]
EC1_ TSEC_ TSEC_
GTX_ 1588_ALARM1588_TRIG AK
CLK125 _OUT[2] _IN[2]
AL
RSRV
[AL1]
RSRV
[AL2]
RSRV
[AL3]
GVDD
[61]
RSRV
[AL5]
RSRV
[AL6]
GND
[69]
MDQ MDQ GVDD MDM
[49] [48] [62]
[6]
IRQ
[11]
GND
[77]
IIC2_
SDA
IIC4_
SDA
OVDD
[4]
SCAN_
MODE
IO_
VSEL
[0]
DMA1_
DACK
[0]
OVDD
[8]
GPIO
[0]
UART1_ SHDC_
SOUT CLK
USB1_
VDD_
3P3
USB1_
AGND
USB1_ USB2_
VDD_1P8 VDD_1P8
_DECAP _DECAP
USB2_
AGND
GND
[91]
TSEC_
1588_PULSE
_OUT[1]
LVDD
[3]
EMI1_
MDIO
EC2_
GTX_
CLK125
GND
[104]
TSEC_ TSEC_
1588_CLK 1588_TRIG AL
_IN _IN[1]
AM
RSRV GVDD RSRV
[AM1] [63] [AM3]
RSRV
[AM4]
GND
[68]
RSRV RSRV GVDD MDQS MDQS
[AM6] [AM7] [64]
[6]
[6]
GND
[76]
NC
[AM12]
IRQ
[7]
IIC3_ IIC2_
SDA SCL
EVT
[4]
GND
[83]
IO_
VSEL
[3]
CKSTP_
OUT
GPIO
[2]
GND
[90]
UART1_ SDHC_ USB_
RTS
DAT CLKIN
[2]
USB1_
AGND
USB1_
IBIAS_
REXT
USB2_
IBIAS_
REXT
USB2_
AGND
SPI_CS
[3]
TSEC_
1588_CLK_
OUT
EC_XTRNL
_TX_STMP
[1]
GND
[105]
EC1_
RXD
[3]
EC1_
RX_DV
LVDD
[7]
EC1_
RX_CLK
AM
AN
RSRV
[AN1]
RSRV
[AN2]
GND
[67]
RSRV RSRV GVDD
[AN4] [AN5] [67]
MDQ
[54]
MDQ
[55]
GND
[75]
MDQ
[50]
MDQ GVDD NC IIC1_
[51] [66] [AN13] SDA
GND
[82]
EVT
[2]
TDI
OVDD TMP_ GPIO
[6] DETECT [3]
DMA1_
DDONE
[0]
OVDD UART2_
[1] SIN
RTC
USB2_ USB2_ USB2_ USB2_ SPI_CS
AGND AGND AGND AGND [0]
GND
[101]
EC2_
GTX_CLK
EC2_
RXD
[2]
LVDD
[4]
EC1_
RXD
[2]
EC1_
RXD
[1]
EC1_
RXD AN
[0]
AP
RSRV
[AP1]
RSRV
[AP2]
RSRV GVDD
[AP3] [68]
RSRV
[AP5]
RSRV
[AP6]
GND
[74]
RSRV MDQ GVDD NC MDQ
[AP8] [60] [65] [AP11] [63]
GND
[81]
NC
[AP14]
TDO
OVDD
[11]
PORESET
IO_
VSEL
[1]
GND
[88]
DMA2_ DMA1_ UART1_ GND
DDONE DREQ
[0] [0]
CTS
[94]
SDHC
_DAT
USB2_
AGND
USB2_
UDM
USB2_ USB2_
UDP AGND
CVDD
[2]
[0]
EC2_
TXD
[2]
LVDD
[2]
EC2_
RXD
[1]
EC2_
RXD
[3]
GND
[99]
EC1_
GTX_
CLK
EC1_
TXD
[3]
AP
AR
RSRV
[AR1]
GVDD
[42]
RSRV
[AR3]
RSRV
[AR4]
GND
[73]
RSRV RSRV GVDD
[AR6] [AR7] [15]
MDQ
[61]
MDQ
[57]
GND
[80]
MDQ
[62]
MDQ
[59]
GVDD
[59]
MDVAL
GND
[92]
HRESET
GND
[86]
TRST
TMS
ASLEEP
TCK
UART1_ OVDD
SIN [12]
USB1_
AGND
USB1_ USB1_
AGND AGND
USB1_ SPI_CS
AGND [2]
EC2_
TXD
[1]
EC2_
TX_EN
GND
[95]
EC2_
RX_
DV
EC1_
TXD
[1]
LVDD
[6]
EC1_
TX_EN
AR
AT
RSRV
[AT1]
RSRV
[AT2]
RSRV
[AT3]
RSRV
[AT4]
RSRV
[AT5]
RSRV
[AT6]
RSRV
[AT7]
RSRV
[AT8]
MDQ
[56]
MDM
[7]
MDQS MDQS
[7] [7]
MDQ
[58]
NC
[AT14]
OVDD
[9]
RESET_ POVDD
REQ
AVDD_
CC2
RSRV
[AT19]
AVDD_
PLAT
TEST
SEL_
GND
[93]
SDHC
SYSCLK _DAT
[1]
USB1_ USB1_ USB1_ USB1_
AGND UDM UDP AGND
SPI_
MOSI
EC2_
TXD
[0]
EC2_
TXD
[3]
EC2_
RXD
[0]
EC2_
RX_
CLK
EC1_
TXD
[2]
EC1_
TXD
[0]
GND
[103]
AT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Signal Groups
OVDD I/O Supply Voltage
SVDD SerDes Core Power Supply
AVDD_
SRDS1
SerDes 1 PLL Supply Voltage
SENSE-
VDD
Core Group A Voltage Sense
LVDD I/O Supply Voltage
XVDD SerDes Transcvr Pad Supply
AVDD_
SRDS2
SerDes 2 PLL Supply Voltage
SENSE-
VDD_CB
Core Group B Voltage Sense
GVDD DDR DRAM I/O Supply
CVDD SPI Voltage Supply
VDD_
CA_CB_PL
Core A, B and Platform Supply
Voltage
VDD_
CB
Core Group B Supply Voltage
AVDD_
PLAT
AVDD_
CC
Platform PLL Supply Voltage VDD_SCEAN_SCEB- _PLCore A, B and Platform Voltage Sense
Core PLL Supply Voltage
RSRV Reserved
BVDD Local Bus I/O Supply
POVDD Fuse Programming Override Supply
Figure 2. 1295 BGA Ball Map Diagram (Top View)
P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2
4 Freescale Semiconductor

No Preview Available !

Pin Assignments and Reset States
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
A
RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV MDQ MDQ MDM MDQ GND
[A2] [A3] [A4] [A5] [A6] [A7] [A8] [A9] [A10] [A11] [A12] [A13] [3] [6] [0] [0] [24]
B
RSRV GVDD RSRV RSRV
[B1] [1] [B3] [B4]
GND
[2]
RSRV RSRV GVDD RSRV RSRV
[B6] [B7] [2] [B9] [B10]
GND
[7]
RSRV RSRV GVDD MDQ
[B12] [B13] [3]
[7]
MDQS
[0]
MDQ
[5]
GND
[31]
C
RSRV RSRV GND
[C] [C2] [1]
RSRV RSRV GVDD RSRV
[C4] [C5] [6] [C7]
MDQ
[16]
GND
[6]
MDQ
[21]
MDQ GVDD RSRV MDQ
[20] [5] [C13] [2]
GND MDQS MDQ GVDD
[14] [0] [4] [4]
D
RSRV RSRV RSRV GVDD RSRV RSRV
[D1] [D2] [D3] [7] [D5] [D6]
GND MDQS MDQS GVDD MDM
[5] [2] [2] [8] [2]
MDQ
[17]
GND
[13]
MDM
[1]
MDQ GVDD MDQ
[8] [9] [1]
NC
[D18]
E
RSRV GVDD RSRV RSRV GND
[E1] [12] [E3] [E4]
[4]
MDQ
[22]
MDQ GVDD MDQ
[23] [11] [18]
MDQ
[19]
GND
[12]
MDQ
[10]
MDQ GVDD MDQ
[14] [10] [13]
NC
[E16]
GND
[25]
LAD
[28]
F RSRV RSRV GND RSRV RSRV GVDD MDQ MDQ GND MDQ MDQ GVDD MDQ MDQS GND MDQ LAD LAD
[F1] [F2] [3] [F4] [F5] [13] [24] [29] [11] [28] [25] [14] [15] [1] [36] [12] [31] [29]
G RSRV RSRV RSRV GVDD RSRV RSRV GND MDQS MDQS GVDD MDM MDQ
[G1] [G2] [G3] [16] [G5] [G6] [10] [3] [3] [17] [3] [11]
GND MDQS MDQ GVDD GND
[35] [1] [9] [18] [231]
LA
[31]
H RSRV GVDD RSRV RSRV GND RSRV MDQ GVDD MDQ MDQ
[H1] [21] [H3] [H4] [9] [H6] [30] [20] [31] [26]
GND NC
NC GVDD NC
[37] [H12] [H13] [19] [H15]
LDP
[3]
LDP BVDD
[2] [9]
J
RSRV RSRV GND
[J1] [J2] [8]
RSRV MECC GVDD MECC MECC GND
[J4] [1] [22] [5] [4] [38]
MDQ
[27]
NC
[J11]
GVDD NC
[25] [J13]
NC
[J14]
LAD
[30]
LWE
[2]
LAD
[15]
LAD
[13]
K
RSRV RSRV RSRV GVDD MDQS MDQS GND
[K1] [K2] [K3] [24]
[8]
[8] [39]
MDM MECC GVDD NC
[8] [0] [23] [K11]
NC
[K12]
NC
[K13]
NC
[K14]
LWE SENSE- SENSE- LAD
[3] VDD_CA GND_CA [14]
_PL _PL
L RSRV GVDD RSRV RSRV GND
[L1] [25] [L3] [L4] [40]
MA
[15]
MECC
[6]
GVDD
[26]
MECC
[7]
MECC VDD
[2] _CA_PL
[1]
GND
[230]
VDD
_CA_PL
[2]
GND
[141]
VDD
_CA_PL
[3]
GND
[98]
VDD
_CA_PL
[4]
GND
[32]
M RSRV RSRV GND RSRV RSRV GVDD MA
[M1] [M2] [41] [M4] [M5] [27] [14]
MBA
[2]
GND
[45]
MECC
[3]
GND
[113]
VDD
_CA_PL
[9]
GND
[127]
VDD
_CA_PL
[10]
GND
[142]
VDD
_CA_PL
[11]
GND
[157]
VDD
_CA_PL
[12]
N RSRV RSRV RSRV GVDD RSRV
[N1] [N2] [N3] [28] [N5]
MA
[12]
GND
[44]
MAPAR_ MCKE
ERR [3]
GVDD
[29]
VDD
_CA_PL
[17]
GND
[126]
VDD
_CA_PL
[19]
GND VDD
[N14] _CA_PL
[19]
GND
[156]
VDD
_CA_PL
[20]
GND
160]
P RSRV GVDD RSRV RSRV GND
[P1] [31] [P3] [P4] [43]
MA
[9]
MA
[11]
GVDD MCKE MCKE
[30] [2]
[0]
GND
[113]
VDD
_CA_PL
[26]
GND
[128]
VDD
_CA_PL
[27]
GND
[P15]
VDD
_CA_PL
[28]
GND
[P17]
VDD
_CA_PL
[29]
R RSRV RSRV GND RSRV RSRV GVDD MA
[R1] [R2] [42] [R4] [R5] [32]
[8]
MA
[7]
GND
[47]
MCKE
[1]
VDD
_CA_PL
[34]
GND
[125]
VDD
_CA_PL
[35]
GND
[139]
VDD
_CA_PL
[36]
GND VDD
[155] _CA_PL
[37]
GND
[161]
T
RSRV RSRV RSRV GVDD RSRV MDIC
[T1] [T2] [T3] [34] [T5] [0]
GND
[48]
MA
[5]
MA
[6]
GVDD
[33]
GND
[115]
VDD
_CA_PL
[43]
GND
[129]
VDD
_CA_PL
[44]
GND
[144]
VDD
_CA_PL
[45]
GND
[159]
VDD
_CA_PL
[46]
U RSRV GVDD GND RSRV GND
[U1] [36] [50] [U4] [49]
MA
[1]
MA GVDD MA
[2] [37] [3]
MA
[4]
VDD
_CA_PL
[51]
GND
[124]
VDD
_CA_PL
[52]
GND
[138]
VDD
_CA_PL
[53]
GND
[154]
VDD
_CA_PL
[54]
GND
[162]
V
RSRV RSRV RSRV RSRV
[V1] [V2] [V3] [V4]
MCK
[1]
MCK GVDD MCK
[1] [38] [2]
MCK
[2]
GND
[54]
GND
[116]
VDD
_CA_PL
[60]
GND
[130]
VDD
_CA_PL
[61]
GND
[145]
VDD
_CA_PL
[62]
GND
[222]
VDD
_CA_PL
[63]
Figure 3. 1295 BGA Ball Map Diagram (Detail View A)
P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
5