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240pin DDR3 SDRAM Unbeffered DIMM
DDR3 SDRAM
Unbuffered DIMMs
Based on 2Gb B-Die
HMT312U6BFR6C
HMT325U6BFR8C
HMT325U7BFR8C
HMT351U6BFR8C
HMT351U7BFR8C
* Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 1.0 / Oct. 2010
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Revision History
Revision No.
0.1
0.2
0.3
1.0
History
Initial Release
Added IDD Specification
Editorial Change
DIMM line-up(1Rx16) added
Draft Date
Dec. 2009
Feb. 2010
Apr. 2010
Oct. 2010
Remark
Rev. 1.0 / Oct. 2010
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Description
Hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM
devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems
such as PCs and workstations.
Feature
• VDD=1.5V +/- 0.075V
• VDDQ=1.5V +/- 0.075V
• VDDSPD=3.0V to 3.6V
• Functionality and operations comply with the DDR3 SDRAM datasheet
• 8 internal banks
• Data transfer rates: PC3-10600, PC3-8500, or PC3-6400
• Bi-directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4
• Supports ECC error correction and detection
• On Die Termination (ODT) supported
• Temperature sensor with integrated SPD (Serial Presence Detect) EEPROM
• RoHS compliant
* This product is in compliance with the RoHS directive.
Ordering Information
Part Number
Density Organization
HMT312U6BFR6C-G7/H9/PB
HMT325U6BFR8C-G7/H9/PB
HMT325U7BFR8C-G7/H9/PB
HMT351U6BFR8C-G7/H9/PB
HMT351U7BFR8C-G7/H9/PB
1GB
2GB
2GB
4GB
4GB
128Mx64
256Mx64
256Mx72
512Mx64
512Mx72
Component Composition
128Mx16(H5TQ2G63BFR)*4
256Mx8(H5TQ2G83BFR)*8
256Mx8(H5TQ2G83BFR)*9
256Mx8(H5TQ2G83BFR)*16
256Mx8(H5TQ2G83BFR)*18
# of
ranks
FDHS
1X
1X
1X
2X
2X
Rev. 1.0 / Oct. 2010
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Key Parameters
MT/s
DDR3-1066
DDR3-1333
DDR3-1600
Grade
-G7
-H9
-PB
tCK
(ns)
1.875
1.5
1.25
CAS
Latency
(tCK)
tRCD
(ns)
7 13.125
9 13.5
11 13.75
tRP
(ns)
13.125
13.5
13.75
tRAS
(ns)
37.5
36
35
tRC
(ns)
50.625
49.5
48.75
CL-tRCD-tRP
7-7-7
9-9-9
11-11-11
Speed Grade
Grade
-G7
-H9
-PB
CL6
800
800
800
Address Table
CL7
1066
1066
1066
Frequency [MHz]
CL8
1066
1066
1066
CL9
1333
1333
CL10
1333
1333
CL11
1600
Remark
Refresh Method
Row Address
Column Address
Bank Address
Page Size
1GB(1Rx16)
8K/64ms
A0-A13
A0-A9
BA0-BA2
2KB
2GB(1Rx8)
8K/64ms
A0-A14
A0-A9
BA0-BA2
1KB
2GB(1Rx8)
8K/64ms
A0-A14
A0-A9
BA0-BA2
1KB
4GB(2Rx8)
8K/64ms
A0-A14
A0-A9
BA0-BA2
1KB
4GB(2Rx8)
8K/64ms
A0-A14
A0-A9
BA0-BA2
1KB
Rev. 1.0 / Oct. 2010
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Pin Descriptions
Pin Name
Description
Pin Name
Description
A0–A15
BA0–BA2
RAS
CAS
WE
S0–S1
CKE0–CKE1
ODT0–ODT1
DQ0–DQ63
CB0–CB7
DQS0–DQS8
DQS0–DQS8
DM0–DM8
CK0–CK1
CK0–CK1
SDRAM address bus
SDRAM bank select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
DIMM Rank Select Lines
SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
DIMM ECC check bits
SDRAM data strobes
(positive line of differential pair)
SDRAM data strobes
(negative line of differential pair)
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
SCL
SDA
SA0–SA2
VDD*
VDDQ*
VREFDQ
VREFCA
VSS
VDDSPD
NC
TEST
RESET
VTT
RSVD
-
I2C serial bus clock for EEPROM
I2C serial bus data line for EEPROM
I2C slave address select for EEPROM
SDRAM core power supply
SDRAM I/O Driver power supply
SDRAM I/O reference supply
SDRAM command/address reference
supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare pins (no connect)
Memory bus analysis tools
(unused on memory DIMMS)
Set DRAMs to Known State
SDRAM I/O termination supply
Reserved for future use
-
*The VDD and VDDQ pins are tied common to a single power-plane on these designs
Rev. 1.0 / Oct. 2010
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