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STF10NK50Z
N-channel 500 V, 0.55 Ω, 9 A Zener-protected SuperMESH™
Power MOSFET in TO-220FP package
Datasheet — production data
Features
Order code VDSS RDS(on) max ID
STF10NK50Z 500 V < 0.7 Ω 9 A
PTOT
30 W
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitance
Applications
Switching application
Description
This device is an N-channel Zener-protected
Power MOSFET developed using
STMicroelectronics’ SuperMESH™ technology,
achieved through optimization of ST’s well
established strip-based PowerMESH™ layout. In
addition to a significant reduction in on-
resistance, this device is designed to ensure a
high level of dv/dt capability for the most
demanding applications.
3
2
1
TO-220FP
Figure 1. Internal schematic diagram
D(2)
G(1)
Table 1. Device summary
Order code
STF10NK50Z
Marking
F10NK50Z
S(3)
AM01476v1
Package
TO-220FP
Packaging
Tube
March 2012
This is information on a product in full production.
Doc ID 022992 Rev 1
1/13
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Contents
Contents
STF10NK50Z
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13 Doc ID 022992 Rev 1

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STF10NK50Z
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
VDS Drain-source voltage
VGS Gate-source voltage
ID Drain current (continuous) at TC = 25 °C
ID
IDM(2)
Drain current (continuous) at TC=100 °C
Drain current (pulsed)
PTOT
Total dissipation at TC = 25 °C
Derating factor
ESD
dv/dt(3)
Gate-source human body model
(C=100 pF, R=1.5 kΩ)
Peak diode recovery voltage slope
VISO
TJ
Tstg
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t=1 s;TC=25 °C)
Operating junction temperature
Storage temperature
1. Limited by maximum junction temperature.
2. Pulse width limited by safe operating area.
3. ISD 9 A, di/dt 200 A/µs,VDD V(BR)DSS, Tj TJMAX
Table 3. Thermal data
Symbol
Parameter
Rthj-case
Rthj-a
Thermal resistance junction-case max
Thermal resistance junction-ambient max
Table 4. Avalanche characteristics
Symbol
Parameter
Avalanche current, repetitive or not-repetitive
IAR (pulse width limited by Tj max)
Single pulse avalanche energy
EAS (starting Tj=25°C, ID=IAR, VDD=50 V)
Electrical ratings
Value
500
± 30
9 (1)
5.7 (1)
36 (1)
30
0.24
4
4.5
2500
-55 to 150
Unit
V
V
A
A
A
W
W/°C
kV
V/ns
V
°C
Value
4.2
62.5
Value
9
230
Unit
°C/W
°C/W
Unit
A
mJ
Doc ID 022992 Rev 1
3/13

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Electrical characteristics
2 Electrical characteristics
STF10NK50Z
(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
V(BR)DSS
Drain-source breakdown
voltage
IDSS
Zero gate voltage drain
current (VGS = 0)
V(BR)GSO
Gate-source breakdown
voltage (ID = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS(th) Gate threshold voltage
RDS(on)
Static drain-source
on-resistance
Test conditions
ID = 1 mA, VGS= 0
VDS = 500 V
VDS = 500 V, TC = 125 °C
IGS = ±1 mA
VGS = ±20 V
VDS= VGS, ID = 100 µA
VGS= 10 V, ID= 4.5 A
Min.
500
±30
3
Typ.
3.75
0.55
Max.
1
50
±10
4.5
0.7
Unit
V
µA
µA
V
µA
V
Ω
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25 V, f=1 MHz, VGS=0
1219
- 159 -
40
pF
pF
pF
Coss
(1)
eq .
Equivalent output
capacitance
VGS=0, VDS =0 to 400 V
- 806 - pF
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD=400 V, ID = 9 A
VGS =10 V
See Figure 15
39.2
- 7.42 -
20.7
nC
nC
nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
inceases from 0 to 80% VDSS
4/13 Doc ID 022992 Rev 1

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STF10NK50Z
Table 7. Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay Time
Fall time
Electrical characteristics
Test conditions
VDD=250 V, ID=4.5A,
RG=4.7Ω, VGS=10V
See Figure 16
Min. Typ. Max. Unit
19 ns
--
17 ns
43 ns
--
15 ns
Table 8. Source drain diode
Symbol
Parameter
Test conditions
ISD Source-drain current
ISDM(1) Source-drain current (pulsed)
VSD(2) Forward on voltage
ISD=9 A, VGS=0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD=9 A,
di/dt = 100 A/µs,
VDD=35 V
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD=9 A,
di/dt = 100 A/µs,
VDD=35 V, Tj=150 °C
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Min Typ. Max Unit
- 9A
- 36 A
- 1.6 V
268
- 1.83
13.7
ns
µC
A
343
- 2.6
15.15
ns
µC
A
Table 9. Gate-source Zener diode
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
BVGSO(1) Gate-source breakdown voltage Igs=±1 mA (open drain) 30 - V
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
Doc ID 022992 Rev 1
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