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Si8660/61/62/63
LOW POWER SIX-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
Selectable fail-safe mode
DC to 150 Mbps
Default high or low output
No start-up initialization required
(ordering option)
Wide Operating Supply Voltage Precise timing (typical)
2.5–5.5 V
10 ns propagation delay
Up to 5000 VRMS isolation
1.5 ns pulse width distortion
60-year life at rated working voltage 0.5 ns channel-channel skew
High electromagnetic immunity
2 ns propagation delay skew
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
RoHS-compliant packages
3.5 mA per channel at 100 Mbps
SOIC-16 wide body
Schmitt trigger inputs
SOIC-16 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Ordering Information:
See page 30.
Safety Regulatory Approvals
UL 1577 recognized
VDE certification conformity
Up to 5000 VRMS for 1 minute
IEC 60747-5-2
CSA component notice 5A approval
(VDE0884 Part 2)
IEC 60950-1, 61010-1, 60601-1
EN60950-1
(reinforced insulation)
(reinforced insulation)
CQC certification approval
GB4943.1
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Ordering options include a choice of isolation ratings
(2.5, 3.75 and 5 kV) and a selectable fail-safe operating mode to control the
default output state during power loss. All products >1 kVRMS are safety
certified by UL, CSA, VDE, and CQC, and products in wide-body packages
support reinforced insulation withstanding up to 5 kVRMS.
Rev. 1.5 9/13
Copyright © 2013 by Silicon Laboratories
Si8660/61/62/63

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Si8660/61/62/63
2 Rev. 1.5

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Si8660/61/62/63
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.1. Si866x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 37
10.3. Si866x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 38
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.5
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Si8660/61/62/63
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Operating Temperature*
TA –40 25 125 °C
Supply Voltage
VDD1
2.5
5.5 V
VDD2
2.5
5.5 V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
VDD Undervoltage
Threshold
VDDUV+
VDD1, VDD2 rising
1.95 2.24 2.375 V
VDD Undervoltage
Threshold
VDDUV–
VDD1, VDD2 falling
1.88 2.16 2.325 V
VDD Undervoltage
Hysteresis
VDDHYS
50 70 95 mV
Positive-Going Input
Threshold
VT+
All inputs rising
1.4 1.67 1.9 V
Negative-Going
Input Threshold
VT– All inputs falling
1.0 1.23 1.4 V
Input Hysteresis
High Level Input Voltage
Low Level Input Voltage
High Level Output Volt-
age
VHYS
VIH
VIL
VOH
loh = –4 mA
0.38
2.0
VDD1,VDD2 – 0.4
0.44
4.8
0.50 V
—V
0.8 V
—V
Low Level Output Volt-
age
VOL
lol = 4 mA
— 0.2 0.4 V
Input Leakage Current
Output Impedance1
IL
ZO
— — ±10 µA
— 50 —
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4 Rev. 1.5

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Si8660/61/62/63
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
DC Supply Current (All inputs 0 V or at Supply)
Si8660Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
— 1.2 1.9
— 3.5 5.3
— 8.8 12.3
— 3.7 5.6
Si8661Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
— 1.7 2.7
— 3.4 5.1
— 7.9 11.1
— 4.8 7.2
Si8662Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
— 2.2 3.3
— 3.0 4.5
— 7.5 10.5
— 5.6 8.4
Si8663Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
— 2.6 3.9
— 2.6 3.9
— 6.5 9.1
— 6.5 9.1
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
mA
mA
mA
mA
Si8660Bx, Ex
VDD1
VDD2
— 5.0 7.0 mA
— 4.2 5.9
Si8661Bx, Ex
VDD1
VDD2
— 4.9 6.9 mA
— 4.6 6.4
Si8662Bx, Ex
VDD1
VDD2
— 5.1 7.1 mA
— 4.7 6.6
Si8663Bx, Ex
VDD1
VDD2
— 4.9 6.8 mA
— 4.9 6.8
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
5