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MB91520 Series
32-bit Microcontroller
FR Family FR81S
MB91F522B/D/F/J/K/L,MB91F523B/D/F/J/K/L,
MB91F524B/D/F/J/K/L,MB91F525B/D/F/J/K/L,MB91F526B/D/F/J/K/L*
Data Sheet (Full Production)
Publication Number MB91F526L_DS705-00011 Revision 2.0 Issue Date January 31, 2014

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DataSheet
MB91F526L_DS705-00011-2v0-E, January 31, 2014

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MB91520 Series
32-bit Microcontroller
FR Family FR81S
MB91F522B/D/F/J/K/L,MB91F523B/D/F/J/K/L,
MB91F524B/D/F/J/K/L,MB91F525B/D/F/J/K/L,MB91F526B/D/F/J/K/L*
Data Sheet (Full Production)
DESCRIPTION
The MB91520 series is a Spansion 32-bit microcontroller designed for automotive devices. This series
contains the FR81S CPU which is compatible with the FR family.
Note: FR is a line of products of Spansion Inc.
*:This series is a composition of the kind that adds HB/JB/KB/LB/SB/UB/WB/YB to the end of the
above-mentioned each name of articles of presence, According to Presence of sub-clock, CSV initial value and
LVD initial value.
Please see "ORDERING INFORMATION" for details.
Spansion provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.spansion.com/Support/microcontrollers/Pages/default.aspx
Publication Number MB91F526L_DS705-00011 Revision 2.0 Issue Date January 31, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.

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DataSheet
FEATURES
FR81S CPU Core
· 32-bit RISC, load/store architecture, pipeline 5-stage structure
· Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied (PLL clock
multiplication system))
· General-purpose register : 32 bits × 16 sets
· 16-bit fixed length instructions (basic instruction), 1 instruction per cycle
· Instructions appropriate to embedded applications
· Memory-to-memory transfer instruction
· Bit processing instruction
· Barrel shift order etc.
· High-level language support instructions
· Function entry/exit instructions
· Register content multi-load and store instructions
· Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
· Branch instructions with delay slot
Overhead reduction during branch process
· Register interlock function
Easy assembler writing
· The support at the built-in / instruction level of the multiplier
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
· Interrupt (PC/PS saving)
6 cycles (16 priority levels)
· The Harvard architecture allows simultaneous execution of program and data access.
· Instruction compatibility with the FR Family
· Built-in memory protection function (MPU)
· Eight protection areas can be specified commonly for instructions and the data.
· Control access privilege in both privilege mode and user mode.
· Built-in FPU (floating point arithmetic)
· IEEE754 compliant
· Floating-point register 32-bit × 16 sets
Peripheral functions
· Clock generation (equipped with SSCG function)
· Main oscillation (4MHz to 16MHz)
· Sub oscillation (32kHz to 100kHz) or none sub oscillation
· PLL multiplication rate : 1 to 20 times
· Built-in program flash memory capacity
MB91F522:256+64KB
MB91F523:384+64KB
MB91F524:512+64KB
MB91F525:768+64KB
MB91F526:1024+64KB
· Flash memory for built-in data (WorkFlash) 64KB
· Built-in RAM capacity
· Main RAM
MB91F522:48KB
MB91F523:48KB
MB91F524:64KB
MB91F525:96KB
MB91F526:128KB
· Backup RAM 8KB
2 MB91F526L_DS705-00011-2v0-E, January 31, 2014

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DataSheet
· General-purpose ports:
MB91F52xB 44 sets (No sub oscillation), 42 sets (sub oscillation)
MB91F52xD 56 sets (No sub oscillation), 54 sets (sub oscillation)
MB91F52xF 76 sets (No sub oscillation), 74 sets (sub oscillation)
MB91F52xJ 96 sets (No sub oscillation), 94 sets (sub oscillation)
MB91F52xK 120 sets (No sub oscillation), 118 sets (sub oscillation)
MB91F52xL 152 sets (No sub oscillation), 150 sets (sub oscillation)
Included I2C open drain corresponding ports:16 sets
· External bus interface
· 22-bit address, 16-bit data
· DMA Controller
· Up to 16 channels can be started simultaneously.
· 2 transfer factors (Internal peripheral request and software)
· A/D converter (successive approximation type)
· 12-bit resolution : Max.48ch (32ch+16ch)
· Conversion time : 1μs
· D/A converter (R-2R type)
· 8-bit resolution : 2ch
· External interrupt input: 8 channels × 2 units total 16 channels
· Level ("H" / "L"), or edge detection (rising or falling) enabled
· Multi-function serial communication (built-in transmission/reception FIFO memory) : Max.12 channels
· 5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 CMOS hysteresis input
< UART (Asynchronous serial interface) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· Parity or no parity is selectable.
· Built-in dedicated baud rate generator
· An external clock can be used as the transfer clock
· Parity, frame, and overrun error detection functions provided
· DMA transfer support
<CSIO (Synchronous serial interface) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· SPI supported; master and slave systems supported; 5 to 16, 20, 24, 32-bit data length can be set.
· Built-in dedicated baud rate generator (Master operation)
· An external clock can be entered. (Slave operation)
· Overrun error detection function is provided
· DMA transfer support
· Serial chip select SPI function
<LIN (Asynchronous Serial Interface for LIN) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· LIN protocol revision 2.1 supported
· Master and slave systems supported
· Framing error and overrun error detection
· LIN synch break generation and detection; LIN synch delimiter generation
· Built-in dedicated baud rate generator
· An external clock can be adjusted by the reload counter
· DMA transfer support
· Hard assist function
< I2C >
· 2 channels ch.3 , ch.4 Standard mode/high-speed mode supported.
· 6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode supported.
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· Standard mode (Max. 100kbps) / high-speed mode (Max. 400kbps) supported
· DMA transfer supported (for transmission only)
January 31, 2014, MB91F526L_DS705-00011-2v0-E
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