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Preliminary Datasheet
Specifications in this document are tentative and subject to
RZ/T1 Group
R01DS0228EJ0060
Rev.0.60
Nov 14, 2014
450 MHz/600MHz, MCU with ARM Cortex®-R4F and -M3*1, on-chip FPU, 747/996 DMIPS, up to 1
Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT*1, USB 2.0 high-speed, CAN, various
communications interfaces such as an SPI multi-I/O bus controller, ∆Σ interface, safety functions,
encoder interfaces*1, and security functions*1
Features
On-chip 32-bit ARM Cortex-R4F processor
High-speed realtime control with maximum operating frequency of
450/600 MHz
Capable of 747/996 DMIPS (in operation at 450/600 MHz)
On-chip 32-bit ARM Cortex-R4F (revision r1p4)
Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes
Instruction cache/data cache with ECC: 8 Kbytes per cache
High-speed interrupt
The FPU supports addition, subtraction, multiplication, division,
multiply-and-accumulate, and square-root operations at single-
precision and double-precision.
Harvard architecture with 8-stage pipeline
Supports the memory protection unit (MPU)
ARM CoreSight architecture, includes support for debugging
through JTAG and SWD interfaces
(Oinn-pcrhoidpu3c2ts-biint cAoRrpMoCraotrintegxa-Mn3Rp-IrNoceensgsinoer )
150-MHz operating frequency
On-chip 32-bit ARM Cortex-M3 (revision r2p1)
RISC Harvard architecture with 3-stage pipeline
Supports the memory protection unit (MPU)
Low power consumption
Standby mode, sleep mode, and module stop function
On-chip extended SRAM
Up to 1 Mbyte of the on-chip extended SRAM with ECC
150 MHz
Data transfer
DMAC: 16 channels × 2 units
DMAC for the Ethernet controller: 1 channel
Event link controller
Module operations can be started by event signals rather than by
interrupt handlers.
Linked operation of modules is available even while the CPU is in
the sleep state.
Reset and power supply voltage control
Four reset sources including a pin reset
Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V
(internal)
Clock functions
External clock/oscillator input frequency: 25 MHz
CPU clock frequency: Up to 450/600 MHz
Low-speed on-chip oscillator (LOCO): 240 kHz
Independent watchdog timer
Operated by a clock signal obtained by frequency-dividing the
clock signal from the low-speed on-chip oscillator: Up to 120 kHz
Safety functions
Register write protection, input clock oscillation stop detection,
CRC, IWDTa, and A/D self-diagnosis
An error control module is incorporated to generate a pin signal
output, interrupt, or internal reset in response to errors originating
in the various modules.
Security functions (optional)*2
Boot mode with security through encryption
Encoder interfaces (optional)*3
EnDat 2.2 and BiSS-compliant interfaces
PRBG0320GA-A 17×17mm, 0.8-mm pitch
PLQP0176LD-A 20 x 20mm, 0.4-mm pitch
Various communications interfaces
Ethernet
- EtherCAT slave controller: 2 ports (for products incorporating an
R-IN engine)
- Ether-MAC: 1 port (without the switching function)
or
- Ether-MAC: 1 port (2 ports with the switching function)
USB 2.0 high-speed host/function : 1 channel
CAN (compliant with ISO11898-1): 2 channels (max.)
SCIFA with 16-byte transmission and reception FIFOs: 5 channels
I2C bus interface: 2 channels for transfer at up to 400 kbps
RSPIa: 4 channels
SPIBSC: Provides a single interface for multi-I/O compatible
serial flash memory
External address space
Buses for high-speed data transfer at 75 MHz (max.)
Support for up to 6 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Up to 33 extended-function timers
16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4
channels): Input capture, output compare, PWM waveform output
16-bit CMT (6 channels), 32-bit CMTW (2 channels)
Serial sound interface (1 channel)
■ ∆Σ interface
Up to 4 ΔΣ modulators are connectable externally.
12-bit A/D converters
12 bits × 2 units (max.)
(8 channels for unit 0; 16 channels for unit 1)
Self diagnosis
Detection of analog input disconnection
Temperature sensor for measuring temperature
within the chip
General-purpose I/O ports
5-V tolerance, open drain, input pull-up
Multi-function pin controller
The locations of input/output functions for peripheral modules are
selectable from among multiple pins.
Operating temperature range
Tj = -40°C to +125°C
Note 1.
Note 2.
Note 3.
Optional
Details of these optional functions will only be given after completion of a binding non-disclosure agreement. For details, contact our sales
representative.
For details, contact our sales representative.
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 1 of 51

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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
1. Overview
1.1 Outline of Specifications
This LSI circuit is a high-performance MCU equipped with the ARM Cortex®-R4F processor and Cortex-M3 (for
products incorporating an R-IN engine) processors, and incorporating integrated peripheral functions necessary for
system configuration. Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of
products in different packages.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1
Outline of Specifications (1 / 7)
Classification
CPU
Module/Function
Central processing unit
(Cortex-R4F)
Central processing unit
(Cortex-M3)
(for products
incorporating an R-IN
engine)
FPU
(Cortex-R4F)
Memory
On-chip extended
SRAM with ECC
Operating modes
Clock
Clock generation circuit
Reset
Description
Maximum operating frequency
320-pin FBGA: 600 MHz
176-pin HLQFP: 450 MHz
32-bit CPU Cortex-R4F designed by ARM (core revision r1p4)
Address space: 4 Gbytes
Instruction cache: 8 Kbytes (with ECC with)
Data cache: 8 Kbytes (with ECC with)
Tightly coupled memory (TCM)
ATCM: 512 Kbytes (with ECC with)
BTCM: 32 Kbytes (with ECC with)
Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2
Data arrangement
Instructions: Little endian
Data: Little endian
Memory protection unit (MPU)
Operating frequency: 150 MHz
32-bit CPU Cortex-M3 designed by ARM (core revision r2p1)
Address space: 4 Gbytes
Instruction set: ARMv7-R architecture, so support includes Thumb® and Thumb-2
Data arrangement
Instructions: Little endian
Data: Little endian
Memory protection unit (MPU)
Supports addition, subtraction, multiplication, division, multiply-and-accumulate, and
square-root operations at single- and double-precision.
Registers
32-bit single-word registers: 32 bits ×32
(can be used as 16 double-word registers: 64 bits x 16)
Capacity: Up to 1 Mbyte
150 MHz
SEC-DED (single error correction/double error detection)
Three boot modes
SPI boot mode (for booting up from serial flash memory)
16-bit bus boot mode (NOR Flash)
32-bit bus boot mode (NOR Flash)
The input clock can be selected from an external clock signal or external resonator.
Detection of input clock oscillation stopping
The following clocks are generated.
CPU clock: 450/600 MHz (max.)
System clock: 150 MHz (fixed)
High-speed peripheral module clock: 150 MHz (fixed)
Low-speed peripheral module clock: 75 MHz (fixed)
ADCCLK in the 12-bit A/D converter (S12ADC): 60 MHz (max.)
External bus clock: 75 MHz (max.)
Low-speed on-chip oscillator: 240 kHz (fixed)
RES # pin reset, error control module (ECM) reset, software reset
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 2 of 51

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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.1
Outline of Specifications (2 / 7)
Classification
Low power
Interrupt
External bus
extension
Data transfer
I/O ports
Module/Function
Description
Low power consumption Standby mode (Cortex-R4F)
Sleep mode (Cortex-M3) (for products incorporating an R-IN engine)
Module stop function
Cortex-R4F
vector interrupt
controller (VIC)
Peripheral function interrupts: 272 sources / 274 sources (for products incorporating an
R-IN engine)
External interrupts: 20 sources
(NMI, IRQ0 to IRQ15, ETH0_INT, ETH1_INT, and ETH2_INT pins)
Software interrupts: 1 source
Non-maskable interrupts: 2 sources
Sixteen levels specifiable for the order of priority
Cortex-M3 nested-type
vector interrupt
controller (NVIC)
(only included in
products incorporating
an R-IN engine)
Peripheral function interrupts: 82 sources
External interrupts: 19 sources
(IRQ0 to IRQ15, ETH0_INT, ETH1_INT, and ETH2_INT pins)
Software interrupts: 1 source
Non-maskable interrupts: 1 source
Sixteen levels specifiable for the order of priority
Bus state controller
(BSC)
The external address space is divided into six areas (CS0 to CS5) for management.
The following features settable for each area independently.
Bus size (8, 16, or 32 bits): Available sizes depend on the area.
Number of access wait cycles (different wait cycles can be specified for read and write
access cycles in some areas)
Idle wait cycle insertion (between same area access cycles or different area access
cycles)
Specifying the memory to be connected to each area enables direct connection to
SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or
asynchronous). The address/data multiplexed I/O (MPX) interface is also available.
Outputs a chip select signal (CS0# to CS5#) according to the target area (CS assert or
negate timing can be selected by software)
SDRAM refresh
Auto refresh or self-refresh mode selectable
SDRAM burst access
Direct memory access
controller (DMAC)
2 units (16 channels for unit 0, 16 channels for unit 1)
Transfer modes: Single transfer mode and block transfer mode
Transfer size
Unit 0: 1/2/4/16/32/64 bytes
Unit 1: 1/2/4/16 bytes
Activation sources: Software trigger, external DMA requests (DREQ0 to DREQ2),
external interrupts, and interrupt requests from peripheral functions
General-purpose I/O
ports
320-pin FBGA
I/O pins: 209
Input pins: 9
Pull-up/pull-down resistors: 209
Open-drain outputs: 9
5-V tolerance: 9
176-pin HLQFP
I/O pins: 97
Input pins: 5
Pull-up/pull-down resistors: 97
Open-drain outputs: 5
5-V tolerance: 5
Event link controller (ELC)
Multi-function pin controller (MPC)
87 event signals can be interlinked with the operation of modules.
In particular, the operation of timer modules can be started by input event signals.
Event-linked operation of signals of ports B and E is to be possible.
The locations of input/output functions are selectable from among multiple pins.
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 3 of 51