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NIKO-SEM P-Channel Logic Level Enhancement
Mode Field Effect Transistor
PA102FDG
TO-252
Lead-Free
PRODUCT SUMMARY
V(BR)DSS
RDS(ON)
-20 115m
ID
-10A
D
G
S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current1
TC = 25 °C
TC = 70 °C
Power Dissipation
TC = 25 °C
TC = 70 °C
Operating Junction & Storage Temperature Range
VDS
VGS
ID
IDM
PD
Tj, Tstg
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
TYPICAL
Junction-to-Case
RθJC
Junction-to-Ambient
RθJA
1Pulse width limited by maximum junction temperature.
2Duty cycle 1%
1 :GATE
2 :DRAIN
3 :SOURCE
LIMITS
-20
±12
-10
-6.2
-24
25
9.6
-55 to 150
MAXIMUM
5
110
UNITS
V
V
A
W
°C
UNITS
°C / W
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
LIMITS
UNIT
MIN TYP MAX
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current1
Drain-Source On-State
Resistance1
Forward Transconductance1
V(BR)DSS
VGS(th)
IGSS
IDSS
VGS = 0V, ID = -250µA
-20
VDS = VGS, ID = -250µA
-0.45 -0.8
VDS = 0V, VGS = ±12V
VDS = -16V, VGS = 0V
VDS = -13.2V, VGS = 0V, TJ = 125 °C
V
-1.2
±100 nA
-1
µA
-10
ID(ON)
RDS(ON)
gfs
VDS = -5V, VGS = -4.5V
VGS = -2.5V, ID =-2A
VGS = -4.5V, ID = -3A
VDS = -5V, ID = -3A
-24 A
124 180
m
93 115
4.4 S
NOV-05-2004
1

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NIKO-SEM P-Channel Logic Level Enhancement
Mode Field Effect Transistor
PA102FDG
TO-252
Lead-Free
DYNAMIC
Input Capacitance
Output Capacitance
Ciss
Coss VGS = 0V, VDS = -6V, f = 1MHz
430
235
Reverse Transfer Capacitance
Total Gate Charge2
Gate-Source Charge2
Gate-Drain Charge2
Turn-On Delay Time2
Rise Time2
Turn-Off Delay Time2
Fall Time2
Crss
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
VDS = 0.5V(BR)DSS, VGS = -4.5V,
ID = -3A
VDD = -10V
ID -1A, VGS = -5V, RG = 6
95
7.6 10
3.2
2
25
60
70
60
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current
IS
Pulsed Current3
ISM
Forward Voltage1
VSD
1Pulse test : Pulse Width 300 µsec, Duty Cycle 2 .
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
IF = -10A, VGS = 0V
-10
-24
-1.2
pF
nC
nS
A
V
REMARK: THE PRODUCT MARKED WITH PA102FDG, DATE CODE or LOT #
Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.
NOV-05-2004
2

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NIKO-SEM P-Channel Logic Level Enhancement
Mode Field Effect Transistor
PA102FDG
TO-252
Lead-Free
Body Diode Forward Voltage Variation with Source Current and Temperature
10
V GS= 0V
1
T A = 125° C
0.1
0.01 25° C -55° C
0.001
0.0001
0
0.2 0.4 0.6 0.8 1.0
-VSD - Body Diode Forward Voltage(V)
1.2
NOV-05-2004
3