Dual, 16-Bit, 125 MSPS Serial LVDS,
1.8 V Analog-to-Digital Converter
1.8 V supply operation
Low power: approximately 150 mW/channel at 125 MSPS,
2 V p-p input range (typical)
SNR/SFDR at 69.5 MHz
77.5 dBFS/88 dBc, 2.0 V p-p input range (typical)
79.3 dBFS/84 dBc, 2.8 V p-p input range (typical)
DNL = ±0.7 LSB; INL = ±4.0 LSB (typical, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.4 LSB (typical, 2.8 V p-p input span)
Serial LVDS, two data lanes per ADC channel
500 MHz full power analog bandwidth
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable output clock and data alignment
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Handheld scope meters
Portable medical imaging and ultrasound
The AD9655 is a dual, 16-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. External reference or driver components are not
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO)
for capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
1 TO 8
SCLK/ SDIO/ CSB
Individual channel power-down is supported. The AD9655
typically consumes less than 2 mW in serial port interface (SPI)
power-down mode. The available digital test pat-terns include
built-in deterministic and pseudorandom patterns, along with
custom user-defined test patterns entered via the SPI.
The AD9655 is available in an RoHS-compliant, 32-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This device is protected by a U.S. patent.
1. Small Footprint.
Two ADCs are contained in a small, space-saving package.
2. Pin Compatible.
The AD9655 is pin compatible to the AD9645 14-bit and
AD9635 12-bit dual ADCs.
3. Ease of Use.
A DCO operates at frequencies of up to 500 MHz and
supports double data rate (DDR) operation.
4. User Flexibility.
The SPI control offers a wide range of flexible features to
meet specific system requirements.
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