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Data Sheet
Dual, 16-Bit, 125 MSPS Serial LVDS,
1.8 V Analog-to-Digital Converter
AD9655
FEATURES
1.8 V supply operation
Low power: approximately 150 mW/channel at 125 MSPS,
2 V p-p input range (typical)
SNR/SFDR at 69.5 MHz
77.5 dBFS/88 dBc, 2.0 V p-p input range (typical)
79.3 dBFS/84 dBc, 2.8 V p-p input range (typical)
Linearity
DNL = ±0.7 LSB; INL = ±4.0 LSB (typical, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.4 LSB (typical, 2.8 V p-p input span)
Serial LVDS, two data lanes per ADC channel
500 MHz full power analog bandwidth
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Clock divider
Programmable output clock and data alignment
Standby mode
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging and ultrasound
Radar/LIDAR
GENERAL DESCRIPTION
The AD9655 is a dual, 16-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. External reference or driver components are not
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO)
for capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided.
Rev. 0
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VINA+
VINA–
VCM
VINB+
VINB–
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD9655
16-BIT
PIPELINE
ADC
16-BIT
PIPELINE
ADC
REFERENCE
16
16
16
16
SERIAL PORT
INTERFACE
1 TO 8
CLOCK DIVIDER
D0A+
D0A–
D1A+
D1A–
D0B+
D0B–
D1B+
D1B–
DCO+
DCO–
FCO+
FCO–
SCLK/ SDIO/ CSB
DFS PDWN
CLK+ CLK–
Figure 1.
Individual channel power-down is supported. The AD9655
typically consumes less than 2 mW in serial port interface (SPI)
power-down mode. The available digital test pat-terns include
built-in deterministic and pseudorandom patterns, along with
custom user-defined test patterns entered via the SPI.
The AD9655 is available in an RoHS-compliant, 32-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This device is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint.
Two ADCs are contained in a small, space-saving package.
2. Pin Compatible.
The AD9655 is pin compatible to the AD9645 14-bit and
AD9635 12-bit dual ADCs.
3. Ease of Use.
A DCO operates at frequencies of up to 500 MHz and
supports double data rate (DDR) operation.
4. User Flexibility.
The SPI control offers a wide range of flexible features to
meet specific system requirements.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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AD9655
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 8
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 12
VREF = 1.0 V ................................................................................. 12
VREF = 1.4 V ................................................................................. 15
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
Analog Input Considerations.................................................... 19
Voltage Reference ....................................................................... 20
REVISION HISTORY
1/15—Revision 0: Initial Version
Data Sheet
Clock Input Considerations...................................................... 22
Power Dissipation and Power-Down Mode ........................... 23
Digital Outputs and Timing ..................................................... 24
Output Test Modes..................................................................... 27
Serial Port Interface (SPI).............................................................. 28
Configuration Using the SPI..................................................... 28
Hardware Interface..................................................................... 29
Configuration Without the SPI ................................................ 29
SPI Accessible Features.............................................................. 29
Memory Map .................................................................................. 30
Reading the Memory Map Register Table............................... 30
Memory Map Register Table..................................................... 31
Memory Map Register Descriptions........................................ 34
Applications Information .............................................................. 36
Design Guidelines ...................................................................... 36
Power and Ground Guidelines ................................................. 36
Clock Stability Considerations ................................................. 36
Exposed Pad Thermal Heat Slug Recommendations............ 36
VCM............................................................................................. 36
Reference Bypassing................................................................... 36
SPI Port ........................................................................................ 36
Outline Dimensions ....................................................................... 37
Ordering Guide .......................................................................... 37
Rev. 0 | Page 2 of 37

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Data Sheet
AD9655
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p full-scale differential input mode, internal reference voltage (VREF) = 1.0 V, input amplitude
(AIN) = −1.0 dBFS, 125 MSPS, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Gain Error
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Common-Mode Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
AVDD
DRVDD
IAVDD3
IDRVDD (ANSI-644 Mode)3
IDRVDD (Reduced Range Mode)3
TOTAL POWER CONSUMPTION
Sine Wave Input (Two Channels, Including Output Drivers ANSI-644 Mode)
Sine Wave Input (Two Channels, Including Output Drivers Reduced Range Mode)
Power-Down
Standby4
Temperature
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Min Typ Max Unit
16 Bits
Guaranteed2
0.2
0.1
3.4
0.4
±0.7
±4.0
% FSR
% FSR
% FSR
% FSR
LSB
LSB
−23 ppm/°C
0.9 ppm/°C
1.0 V
2.9 mV
7.5 kΩ
2.7 LSB rms
2 V p-p
0.9 V
0.5 1.2 V
1.9 kΩ
6.6 pF
1.7 1.8 1.9 V
1.7 1.8 1.9 V
93 mA
73 mA
62 mA
299 mW
279 mW
2 mW
142 mW
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 No missing codes guaranteed if Register 0x18 = 0x04 (default, no digital scaling of the output).
3 Measured with a low input frequency, −1 dBFS sine wave on both channels, DDR operation, and two-lane operation.
4 Standby mode can be controlled via the SPI.
Rev. 0 | Page 3 of 37

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AD9655
Data Sheet
AVDD = 1.8 V, DRVDD = 1.8 V, 2.8 V p-p full-scale differential input mode, VREF = 1.4 V, AIN = −1.0 dBFS, 125 MSPS, unless otherwise noted.
Table 2.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Gain Error
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1.4 V Mode)
Load Regulation at 1.0 mA (VREF = 1.4 V)
Input Resistance
INPUT-REFERRED NOISE
VREF = 1.4 V
ANALOG INPUTS
Differential Input Voltage (VREF = 1.4 V)
Common-Mode Voltage
Common-Mode Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
AVDD
DRVDD
IAVDD3
IDRVDD (ANSI-644 Mode)3
IDRVDD (Reduced Range Mode)3
TOTAL POWER CONSUMPTION
Sine Wave Input (Two Channels, Including Output Drivers ANSI-644 Mode)
Sine Wave Input (Two Channels, Including Output Drivers Reduced Range Mode)
Power-Down
Standby4
Temperature Min
16
Typ Max
Unit
Bits
Full Guaranteed2
Full −0.12 +0.2 +0.48 % FSR
Full −0.2 +0.1 +0.33 % FSR
Full −2.4 +2.8 +8.2 % FSR
Full −1.2 +0.4 +1.9 % FSR
Full
−0.99
+1.43 LSB
25°C ±0.7 LSB
Full −8.5 +8.5 LSB
25°C ±3.4 LSB
Full −66 ppm/°C
Full 0.9 ppm/°C
Full 1.37 1.38 1.41 V
25°C 186 mV
25°C 7.5 kΩ
25°C 2 LSB rms
Full 2.8 V p-p
Full 0.9 V
25°C 0.7
1.0 V
25°C 1.9 kΩ
25°C 6.6 pF
Full 1.7 1.8 1.9 V
Full 1.7 1.8 1.9 V
Full 101 111 mA
Full
73 79
mA
Full
62 68
mA
Full 313 342 mW
Full 293 322 mW
Full
24
mW
Full 155 172 mW
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 No missing codes guaranteed if Register 0x18 = 0x04 (default, no digital scaling of the output).
3 Measured with a low input frequency, −1 dBFS sine wave on both channels, DDR operation, and two-lane operation.
4 Standby mode can be controlled via the SPI.
Rev. 0 | Page 4 of 37

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Data Sheet
AD9655
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p full-scale differential input mode, VREF = 1.0 V, AIN = −1.0 dBFS, 125 MSPS, unless otherwise noted.
Table 3.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 100.1 MHz, fIN2 = 102.1 MHz
CROSSTALK2
CROSSTALK (OVERRANGE CONDITION)3
ANALOG INPUT BANDWIDTH, FULL POWER
Temperature Min Typ Max Unit
25°C
25°C
25°C
25°C
25°C
25°C
77.9 dBFS
77.9 dBFS
77.5 dBFS
76.6 dBFS
75.6 dBFS
71.0 dBFS
25°C
25°C
25°C
25°C
25°C
25°C
77.5 dBFS
77.1 dBFS
77.1 dBFS
76.5 dBFS
75.2 dBFS
68.0 dBFS
25°C
25°C
25°C
25°C
25°C
25°C
12.6 Bits
12.5 Bits
12.5 Bits
12.4 Bits
12.2 Bits
11 Bits
25°C
25°C
25°C
25°C
25°C
25°C
88 dBc
86 dBc
88 dBc
91 dBc
85 dBc
70 dBc
25°C
25°C
25°C
25°C
25°C
25°C
−88 dBc
−86 dBc
−88 dBc
−91 dBc
−85 dBc
−70 dBc
25°C
25°C
25°C
25°C
25°C
25°C
−95 dBc
−99 dBc
−92 dBc
−91 dBc
−89 dBc
−80 dBc
25°C
90 dBc
25°C
−104
dB
25°C
−100
dB
25°C
500 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Crosstalk is measured at 69.5 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. Measurements are taken using a less dense
board to demonstrate the AD9655 crosstalk performance, not board limitations.
3 Overrange condition is specified as being 3 dB above the full-scale input range.
Rev. 0 | Page 5 of 37