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PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
DATASHEET
932SQ420D
General Description
The 932SQ420D is a main clock synthesizer for
Romley-generation Intel based server platforms. The
932SQ420D is driven with a 25 MHz crystal for maximum
performance. It generates CPU outputs of 100 or 133.33
MHz.
Recommended Application
CK420BQ
Output Features
4 - HCSL CPU outputs
4 - HCSL Non-Spread SAS/SRC outputs
3 - HCSL SRC outputs
1 - HCSL DOT96 output
1 - 3.3V 48M output
5 - 3.3V PCI outputs
1- 3.3V REF output
Block Diagram
Features/Benefits
0.5% down spread capable on CPU/SRC/PCI
outputs/Lower EMI
64-pin TSSOP and MLF packages/Space Savings
Key Specifications
Cycle to cycle jitter: CPU/SRC/NS_SRC/NS_SAS <
50ps.
Phase jitter: PCIe Gen2 < 3ps rms, Gen3 < 1ps rms
Phase jitter: QPI 9.6GB/s < 0.2ps rms
Phase jitter: NS-SAS < 0.4ps rms using raw phase data
Phase jitter: NS-SAS < 1.3ps rms using Clk Jit Tool 1.6.3
X1_25
X2
CPU_SRC_PCI
PLL (SS)
Low Drift non-SS
PLL
<500ps LTJ
Non-SS PLL
CPU(3:0)
SRC(2:0)
/3 PCI(4:0)
NS_SAS(1:0)
NS_SRC(1:0)
DOT96
/2 48M
Test_Sel
Test_Mode
100M_133M#
CKPWRGD#/PD
SMBDAT
SMBCLK
Logic
14.31818MHz
Non-SS PLL
REF14M
IREF
IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
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932SQ420D
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932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
Pin Configuration - 64TSSOP
SMBCLK 1
64 SMBDAT
GND14 2
63 VDDCPU
AVDD14 3
62 CPU3T
VDD14 4
vREF14_3x/TEST_SEL 5
61 CPU3C
60 CPU2T
GND14 6
59 CPU2C
GNDXTAL 7
58 GNDCPU
X1_25 8
57 VDDCPU
X2_25 9
56 CPU1T
VDDXTAL 10
55 CPU1C
GNDPCI 11
54 CPU0T
VDDPCI 12
53 CPU0C
PCI4_2x 13
52 GNDNS
PCI3_2x 14
51 AVDD_NS_SAS
PCI2_2x 15
50 NS_SAS1T
PCI1_2x 16
49 NS_SAS1C
PCI0_2x 17
48 NS_SAS0T
GNDPCI 18
VDDPCI 19
47 NS_SAS0C
46 GNDNS
VDD48 20
^48M_2x/100M_133M# 21
45 VDDNS
44 NS_SRC1T
GND48 22
43 NS_SRC1C
GND96 23
42 NS_SRC0T
DOT96T 24
41 NS_SRC0C
DOT96C 25
40 IREF
AVDD96 26
39 GNDSRC
TEST_MODE 27
38 AVDD_SRC
CKPWRGD#/PD 28
37 VDDSRC
VDDSRC 29
36 SRC2T
SRC0T 30
SRC0C 31
35 SRC2C
34 SRC1T
GNDSRC 32
33 SRC1C
64-TSSOP
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldown
Spread Spectrum Control
SS_Enable
(B1 b0)
0
1
CPU, SRC &
PCI
OFF
ON
Power Group Pin Numbers
MLF
TSSOP
VDD GND VDD GND
Desc ription
57 56 3
2 14MHz PLL Analog
58 60 4
6 REF14M Output and Logic
64 61 10
7 25MHz XTAL
2, 9 1, 8 12, 19 11, 18 PCI Outputs and Logic
10 12 20 22 48MHz Output and Logic
16 13 26 23 96MHz PLL Analog, Output and Logic
19, 27 22 29, 37 32 SRC Outputs and Logic
28 29 38 39 SRC PLL Analog
35
41
47, 53
36 45
42 51
48 57,63
46 Non-Spreading Differential Outputs & Logic
52 NS-SAS/SRC PLL Analog
58 CPU Outputs and Logic
932SQ420 Power Down Functionality
CK PW RG D#/PD
1
0
Differential
Outputs
HI-Z1
Single-ended
Outputs
Low
Runn ing
Single ended
Outputs w/Latch
Low2
1. Hi-Z on the differential outputs will result in both True and
Complement being low due to the termination network
2. These outputs are Hi-Z after VDD is applied and before the first
assertion of CKPWRGD #.
IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
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932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
Pin Descriptions - 64 TSSOP
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PIN N AME
SMBCLK
GN D14
AVDD14
VDD1 4
vRE F14_ 3x/ TE ST_S EL
GN D14
GN DXTAL
X1_ 25
X2_ 25
VDDXTAL
GN DPCI
VDDPCI
PCI4 _2x
PCI3 _2x
PCI2 _2x
PCI1 _2x
PCI0 _2x
GN DPCI
VDDPCI
VDD4 8
^48M _2x/100 M_13 3M#
GN D48
GN D96
DO T9 6T
DO T9 6C
AVDD96
TEST_ MO DE
CKP WRG D# /PD
VDDSRC
TYPE
DESCRIPTION
IN Clock pin of SMBUS circuitry, 5V tolerant
PWR Ground pin for 14MHz output and logic.
PWR Analog power pin for 14MHz PLL
PWR Pow er pin for 14MHz output and logic
I/O
14.318 MH z reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode.
Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down.
PWR Ground pin for 14MHz output and logic.
PWR Ground pin for Crystal Oscillator.
IN Crystal input, Nominally 25.00MHz.
OUT Crystal output, Nominally 25.00MHz.
PWR 3.3V power for the crystal oscillator.
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
PWR 3.3V power for the 48MHz output and logic
3.3V 48MHz output/ 3.3V tolerant CPU frequency select latched input pin. See VilFS and VihFS values for
I/O thresholds. This pin has a weak (~120Kom) internal pull up.
1 = 100MHz, 0 = 133MHz operating frequency
PWR Ground pin for 48MHz output and logic.
PWR Ground pin for DOT96 output and logic.
True clock of differential 96MHz output. These are current mode outputs. These are current mode outputs
OUT and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.
Complementary clock of differential 96MHz output. These are current mode outputs and external 33 ohm
OUT series resistors and 49.9 ohm shunt resistors are required for termination.
PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to
Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an
IN asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs
are stopped.
PWR 3.3V power for the SRC outputs and logic
30 SRC0T
OUT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and
external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.
31 SRC0C
32 GN DSRC
33 SRC1C
OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm
series resistors and 49.9 ohm shunt resistors are required for termination.
PWR Ground pin for SRC outputs and logic.
OUT
Complementary clock of differential SRC output. These are current mode outputs and
series resistors and 49.9 ohm shunt resistors are required for termination.
external 33 ohm
34 SRC1T
OUT
True clock of differential SRC output. These are current mode outputs. These are current mode outputs and
external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.
35 SRC2C
OUT
Complementary clock of differential SRC output. These are current mode outputs and
series resistors and 49.9 ohm shunt resistors are required for termination.
external 33 ohm
36 SRC2T
OUT
True clock of differential SRC output. These are current mode outputs. These are current mode outputs and
external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.
37 VDDSRC
38 AVDD_SRC
39 GN DSRC
40 IREF
PWR 3.3V power for the SRC outputs and logic
PWR 3.3V power for the SRC PLL analog circuits
PWR Ground pin for SRC outputs and logic.
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a
OUT fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard
va lue .
IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
3
932SQ420D
REV J 010715