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Multiphase PWM Regulator for IMVP-6.5™ Mobile
CPUs and GPUs
ISL62883C
The ISL62883C is a multiphase PWM buck regulator for
miroprocessor or graphics processor core power supply.
The multiphase buck converter uses interleaved phase to
reduce the total output voltage ripple with each phase
carrying a portion of the total load current, providing
better system performance, superior thermal
management, lower component cost, reduced power
dissipation, and smaller implementation area. The
ISL62883C uses two integrated gate drivers and an
external gate driver to provide a complete solution. The
PWM modulator is based on Intersil's Robust Ripple
Regulator (R3) technology™. Compared with traditional
modulators, the R3™ modulator commands variable
switching frequency during load transients, achieving
faster transient response. With the same modulator, the
switching frequency is reduced at light load, increasing
the regulator efficiency.
The ISL62883C can be configured as CPU or graphics
Vcore controller and is fully compliant with IMVP-6.5™
specifications. It responds to PSI# and DPRSLPVR signals
by adding or dropping PWM3 and Phase 2 respectively,
adjusting overcurrent protection threshold accordingly,
and entering/exiting diode emulation mode. It reports
the regulator output current through the IMON pin. It
senses the current by using either discrete resistor or
inductor DCR whose variation over temperature can be
thermally compensated by a single NTC thermistor. It
uses differential remote voltage sensing to accurately
regulate the processor die voltage. The adaptive body
diode conduction time reduction function minimizes
the body diode conduction loss in diode emulation
mode. User-selectable overshoot reduction function
offers an option to aggressively reduce the output
capacitors as well as the option to disable it for users
concerned about increased system thermal stress. In
2-Phase configuration, the ISL62883C offers the FB2
function to optimize 1-Phase performance.
Features
• Programmable 1, 2- or 3-Phase CPU or GPU Mode of
Operation
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Microprocessor Voltage Identification Input
- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Supports PSI# and DPRSLPVR modes
• Superior Noise Immunity and Transient Response
• Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Two Integrated Gate Drivers
• Excellent Dynamic Current Balance
• FB2 Function Optimizes 1-Phase Mode Performance
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 40 Ld 5x5 TQFN Packages
• Pb-Free (RoHS Compliant)
Applications*(see page 42)
• Notebook Core Voltage Regulator
• Notebook GPU Voltage Regulator
Related Literature*(see page 42)
• See AN1460 for ISL62883/ISL62883C Evaluation
Board Application Note “ISL62883EVAL2Z User
Guide”
Load Line Regulation
1.10
1.08
1.06
1.04
1.02
1.00
VIN = 8V
VIN = 12V
VIN = 19V
0.98
0.96
0.94
0.92 0
5 10 15 20 25 30 35 40 45 50 55 60 65
IOUT (A)
March 18, 2010
FN7557.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL62883C
Ordering Information
PART NUMBER
(Note 3)
ISL62883CIRTZ (Note 2)
ISL62883CIRTZ-T (Notes 1, 2)
PART MARKING
62883C IRTZ
62883C IRTZ
TEMP. RANGE
(°C)
-40 to +100
-40 to +100
PACKAGE
(Pb-Free)
40 Ld 5x5 TQFN
40 Ld 5x5 TQFN
PKG.
DWG. #
L40.5x5
L40.5x5
ISL62883CHRTZ (Note 2)
62883C HRTZ
-10 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62883CHRTZ-T (Notes 1, 2) 62883C HRTZ
-10 to +100
40 Ld 5x5 TQFN
L40.5x5
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62883C. For more information on MSL please
see techbrief TB363.
Pin Configuration
ISL62883C
(40 LD TQFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
PGOOD 1
PSI# 2
RBIAS 3
VR_TT# 4
NTC 5
VW 6
COMP 7
FB 8
ISEN3/FB2 9
ISEN2 10
GND PAD
(BOTTOM)
30 BOOT2
29 UGATE2
28 PHASE2
27 VSSP2
26 LGATE2
25 VCCP
24 PWM3
23 LGATE1
22 VSSP1
21 PHASE1
11 12 13 14 15 16 17 18 19 20
2 FN7557.1
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ISL62883C
Functional Pin Descriptions
ISL62883C
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14, 15
16
17
18
19
20
21
22
23
24
SYMBOL
DESCRIPTION
GND
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
PGOOD
Power-Good open-drain output indicating when the regulator is able to supply regulated
voltage. Pull up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
PSI#
Low load current indicator input. When asserted low, indicates a reduced load-current condition.
RBIAS
A resistor to GND sets internal current reference. Use 147kΩ or 47kΩ. The choice of Rbias value,
together with the ISEN2 pin configuration and the external resistance from the COMP pin to
GND, programs the controller to enable/disable the overshoot reduction function and to select
the CPU/GPU mode.
VR_TT# Thermal overload output indicator.
NTC
Thermistor input to VR_TT# circuit.
VW A resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately
300kHz).
COMP
This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the
overcurrent threshold.
FB This pin is the inverting input of the error amplifier.
INSE3/FB2
When the ISL62883C is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual
current sensing for phase 3. When the ISL62883C is configured in 2-phase mode, this pin is
FB2. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode
and is off in 1-phase mode. The components connecting to FB2 are used to adjust the
compensation in 1-phase mode to achieve optimum performance.
ISEN2
Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will
disable Phase 2.
ISEN1 Individual current sensing for phase 1.
VSEN
Remote core voltage sense input. Connect to microprocessor die.
RTN
Remote voltage sensing return. Connect to ground at microprocessor die.
ISUM- and Droop current sense input.
ISUM+
VDD
5V bias power.
VIN Battery supply voltage, used for feed-forward.
IMON
An analog output. IMON outputs a current proportional to the regulator output current.
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each
time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
UGATE1
Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the
Phase-1 high-side MOSFET.
PHASE1
Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to
the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.
VSSP1
Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the
source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1 low-
side MOSFETs.
LGATE1
Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
PWM3
PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase-3
and allow other phases to operate.
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ISL62883C
Functional Pin Descriptions (Continued)
ISL62883C
25
SYMBOL
VCCP
DESCRIPTION
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at
least 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins respectively.
26 LGATE2 Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the
Phase-2 low-side MOSFET.
27 VSSP2 Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2
pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET.
28 PHASE2 Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to
the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.
29 UGATE2 Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the
Phase-2 high-side MOSFET.
30 BOOT2 Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each
time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
31 thru 37
VID0 thru VID input with VID0 = LSB and VID6 = MSB.
VID6
38 VR_ON Voltage regulator enable input. A high level logic signal on this pin enables the regulator.
39 DPRSLPVR Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor
is in deeper sleep mode.
40 CLK_EN# Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is
within 10% of Vboot.
pad BOTTOM The bottom pad of ISL62883C is electrically connected to the GND pin inside the IC.It should
also be used as the thermal pad for heat removal.
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ISL62883C
Block Diagram
VIN VSEN ISEN1 ISEN3 ISEN2 PGOOD CLK_EN#
VDD
VR_ON
PSI#
DPRSLPVR
RBIAS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
RTN
FB
COMP
VW
IMON
ISUM+
ISUM-
MODE
CONTROL
DAC
AND
SOFT-
START
IBAL2
IBAL3
IBAL1
CURRENT
BALANCE
PGOOD &
CLK_EN#
LOGIC
IBAL
PROTECTION FLT
IBAL2 VIN VDAC
WOC OC
VIN
MODULATOR
CLOCK
VDAC
COMP
VW
COMP
IBAL3 VIN VDAC
6µA 54µA 1.20V
1.24V
DRIVER
SHOOT-THROUGH
PROTECTION
DRIVER
+
+
Σ
+
E/A
_
MODULATOR
COMP
IBAL1 VIN VDAC
IDROOP
IMON
+
CURRENT
_ SENSE
MODULATOR
+_
2.5X
+
_
WOC
COMP
CURRENT
COMPARATORS
NUMBER OF
OC PHASES
60µA
ΣGAIN
+
SELECT
+
DRIVER
SHOOT-THROUGH
PROTECTION
DRIVER
ADJ. OCP
THRESHOLD
COMP
VR_TT#
NTC
BOOT2
UGATE2
PHASE2
LGATE2
VSSP2
PWM3
BOOT1
UGATE1
PHASE1
VCCP
LGATE1
VSSP1
GND
5 FN7557.1
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