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SEMICONDUCTOR
80C286
March 1997
High Performance Microprocessor
with Memory Management and Protection
Features
Description
• Compatible with NMOS 80286
• Wide Range of Clock Rates
- DC to 25MHz (80C286-25)
- DC to 20MHz (80C286-20)
- DC to 16MHz (80C286-16)
- DC to 12.5MHz (80C286-12)
- DC to 10MHz (80C286-10)
• Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10)
220mA Maximum (80C286-12)
260mA Maximum (80C286-16)
310mA Maximum (80C286-20)
410mA Maximum (80C286-25)
• High Performance Processor (Up to 19 Times the 8086
Throughput)
• Large Address Space
• 16 Megabytes Physical/1 Gigabyte Virtual per Task
• Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and Operat-
ing Systems
• Two 80C86 Upward Compatible Operating Modes
- 80C286 Real Address Mode
- PVAM
The Harris 80C286 is a static CMOS version of the NMOS
80286 microprocessor. The 80C286 is an advanced, high-
performance microprocessor with specially optimized capa-
bilities for multiple user and multi-tasking systems. The
80C286 has built-in memory protection that supports operat-
ing system and task isolation as well as program and data
privacy within tasks. A 25MHz 80C286 provides up to nine-
teen times the throughput of a standard 5MHz 8086. The
80C286 includes memory management capabilities that
map 230 (one gigabyte) of virtual address space per task
into 224 bytes (16 megabytes) of physical memory.
The 80C286 is upwardly compatible with 80C86 and 80C88
software (the 80C286 instruction set is a superset of the
80C86/80C88 instruction set). Using the 80C286 real
address mode, the 80C286 is object code compatible with
existing 80C86 and 80C88 software. In protected virtual
address mode, the 80C286 is source code compatible with
80C86 and 80C88 software but may require upgrading to
use virtual address as supported by the 80C286’s integrated
memory management and protection mechanism. Both
modes operate at full 80C286 performance and execute a
superset of the 80C86 and 80C88 instructions.
The 80C286 provides special operations to support the effi-
cient implementation and execution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The 80C286 also supports virtual
memory systems by providing a segment-not-present excep-
tion and restartable instructions.
• Compatible with 80287 Numeric Data Co-Processor
• High Bandwidth Bus Interface (25 Megabyte/Sec)
• Available In
- 68 Pin PGA (Commercial, Industrial, and Military)
- 68 Pin PLCC (Commercial and Industrial)
Ordering Information
PACKAGE
PGA
PLCC
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
0oC to +70oC
-40oC to +85oC
10MHz
-
IG80C286-10
5962-
9067801MXC
-
IS80C286-10
12.5MHz
CG80C286-12
IG80C286-12
5962-
9067802MXC
CS80C286-12
IS80C286-12
16MHz
CG80C286-16
-
-
CS80C286-16
IS80C286-16
20MHz
CG80C286-20
-
-
CS80C286-20
IS80C286-20
25MHz
-
-
-
CS80C286-25
-
PKG. NO.
G68.B
G68.B
G68.B
N68.95
N68.95
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
3-68
File Number 2947.2

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Pinouts
80C286
68 LEAD PGA
Component Pad View - As viewed from underside of the component when mounted on the board.
A0 D0
A2 A1
VCC
CLK
A3 RESET
A5 A4
A7 A6
A9 A8
A11 A10
A13 A12
35 37 39 41 43 45 47 49 51
34 36 38 40 42 44 46 48 50 53 52
32 33
55 54
30 31
57 56
28 29
59 58
26 27
61 60
24 25
63 62
22 23
65 64
20 21
67 66
18 19 16 14 12 10 8 6 4 2 68
17 15 13 11 9 7 5 3 1
ERROR NC
NC BUSY
INTR
NC
NMI NC
PEREQ VSS
READY VCC
HLDA HOLD
M / IO
COD / INTA
NC LOCK
PIN 1 INDICATOR
68 LEAD PGA
P.C. Board View - As viewed from the component side of the P.C. board.
NC ERROR
BUSY
NC
NC INTR
NC NMI
VSS PEREQ
VCC READY
HOLD HLDA
COD / INTA
M / IO
LOCK
NC
51 49 47 45 43 41 39 37 35
52 53 50 48 46 44 42 40 38 36 34
54 55
33 32
56 57
31 30
58 59
29 28
60 61
27 26
62 63
25 24
64 65
23 22
66 67
21 20
68 2 4 6 8 10 12 14 16 19 18
1 3 5 7 9 11 13 15 17
D0 A0
A1 A2
CLK
VCC
RESET A3
A4 A5
A6 A7
A8 A9
A10 A11
A12 A13
PIN 1 INDICATOR
3-69

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Pinouts (Continued)
80C286
68 LEAD PLCC
P.C. Board View - As viewed from the component side of the P.C. board.
BHE
NC
NC
S1
S0
PEACK
A23
A22
VSS
A21
A20
A19
A18
A17
A16
A15
A14
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1 51
2 50
3 49
4 48
5 47
6 46
7 45
8 44
9 43
10 42
11 41
12 40
13 39
14 38
15 37
16 36
17 35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
VSS
Functional Diagram
ADDRESS UNIT (AU)
OFFSET
ADDER
SEGMENT
BASES
SEGMENT
LIMIT SEGMENT
CHECKER SIZES
PHYSICAL
ADDRESS
ADDER
ALU
ADDRESS
LATCHES AND DRIVERS
PRE-
FETCHER
PROCESSOR
EXTENSION
INTERFACE
BUS CONTROL
DATA TRANSCEIVERS
6-BYTE
PREFETCH
QUEUE
BUS UNIT (BU)
REGISTERS CONTROL
EXECUTION UNIT (EU)
3 DECODED
INSTRUCTION
QUEUE
INSTRUCTION
DECODER
INSTRUCTION
UNIT (IU)
NMI BUSY
INTR ERROR
A23 - A0,
BHE, M/IO
PEACK
PEREQ
READY,
HOLD,
S1, S0,
COD/INTA,
LOCK, HLDA
D15 - D0
RESET
CLK
VSS
VCC
3-70