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TMP93PW20A
Low Voltage/Low Power
CMOS 16-Bit Microcontroller
TMP93PW20AF
1. Outline and Device Characteristics
The TMP93PW20A is OTP type MCU which includes 128 Kbytes one-time PROM. Using the
adapter-socket, you can write and verify the data for the TMP93CS20 by general EPROM
programmer.
The TMP93PW20A has the same pin-assignment as the TMP93CS20 (Mask ROM type).
Writing the program to built-in PROM, the TMP93PW20A operates as the same way as the
TMP93CS20.
There are differences in the memory mapping area and the memory capacity of the internal
PROM and RAM between the TMP93PW20A and the TMP93CS20. The internal PROM of the
TMP93PW20A is 128 Kbytes, and the internal RAM is 4 Kbytes. The internal ROM of the
TMP93CS20 is 64 Kbytes, and the internal RAM is 2 Kbytes. Memory maps are described as
follows.
030619EBP1
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any
law and regulations.
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
93PW20A-1
2004-02-10

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000000H
0000A0H
0010A0H
Internal I/O
(128 bytes)
Internal RAM
(4 Kbytes)
TMP93PW20A
000000H
0000A0H
0008A0H
Internal I/O
(128 bytes)
Internal RAM
(2 Kbytes)
FE0000H
Internal PROM
(128 Kbytes)
FFFF00H
Interrupt vector table area
(256 bytes)
FFFFFFH
Memory map of TMP93PW20A
Product No.
TMP93PW20A
ROM
OTP 128 Kbytes
RAM
4 Kbytes
FF0000H
Internal ROM
(64 Kbytes)
FFFF00H
Interrupt vector table area
(256 bytes)
FFFFFFH
Memory map of TMP93CS20
Package
P-LQFP144-1616-0.40
Adapter Socket
BM11141
93PW20A-2
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TMP93PW20A
ADTRG (P37)
AN0 to AN7
(P50 to P57)
AVCC
AVSS
VREFH
VREFL
SCK (P60)
SO/SDA (P61)
SI/SCL (P62)
TXD0 (P63)
RXD0 (P64)
SCLK0/ CTS0 (P65)
TXD1 (P80)
RXD1 (P81)
TI0 (P66)
TO1 (P67)
TI2 (P82)
TO3 (P83)
TI4 (P40)
TO4 (P41)
TI6 (P42)
TO6 (P43)
KEY0 to KEY7
(P40 to P47)
10-bit 8 channel
AD
converter
Serial bus
interface
Serial I/O
(Cannel 0)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
CPU (900/L)
WA
BC
DE
HL
IX
IY
IZ
SP
32 bits
SR F
PC
OSC1
Clock Gear
OSC2
Serial I/O
(Channel 1)
8-bit timer
(Timer 0)
8-bit timer
(Timer 1)
8-bit timer
(Timer 2)
8-bit timer
(Timer 3)
16-bit timer
(Timer 4)
16-bit timer
(Timer 6)
Key wakeup
(KEY0 to KEY7)
Real time
counter
4 Kbytes RAM
128 Kbytes ROM
Port 0
Port 1
Port 2
16-bit timer
(Timer 8)
16-bit timer
(Timer A)
Watchdog
timer
Interrupt
controller
LCD driver
VCC [3]
VSS [8]
X1
X2
XT1 (P86)
XT2 (P87)
CLK
ALE
SCOUT (P73)
EA
RESET
RD (P30)
WR (P31)
HWR (P32)
WAIT (P84)
P00 to P07
(AD0 to AD7)
P10 to P17
(AD8/A8 to AD15/A15)
P20 to P27
(A0/A16 to A7/A23)
TI8/INT8 (P70)
TI9/INT9 (P71)
TO8 (P72)
TIA/INTA (P74)
TIB/INTB (P75)
TOA (P76)
NMI (P77)
INT0 to INT4 (P33 to P37)
INT7 (P66)
V1 to V3
C0 to C1
SEG0 to SEG23
SEG24 to SEG39 (P90 to PA7)
COM0 to COM3
Note: The item in parentheses ( ) are the initial setting after reset.
Figure 1.1 TMP93PW20A Block Diagram
93PW20A-3
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TMP93PW20A
2. Pin Assignment and Functions
The assignment of input/output pins for the TMP93PW20A their names and outline functions
are described below.
2.1 Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93PW20AF.
(SEG34) PA2
(SEG35) PA3
(SEG36) PA4
(SEG37) PA5
(SEG38) PA6
(SEG39) PA7
( RD ) P30
VSS
( WR ) P31
( HWR ) P32
(INT0) P33
(INT1) P34
(INT2) P35
(INT3) P36
(INT4/ ADTRG ) P37
VREFH
VREFL
(AN7) P57
(AN6) P56
(AN5) P55
(AN4) P54
(AN3) P53
(AN2) P52
(AN1) P51
(AN0) P50
AVCC
AVSS
VSS
VCC
(AD0) P00
(AD1) P01
(AD2) P02
(AD3) P03
(AD4) P04
(AD5) P05
(AD6) P06
108
109
110 105
115
120
125
130
135
140
144
1
5
100
10
95 90 85
TMP93PW20AF
LQFP144
Top view
15 20 25
80
30
73
72
75
70
65
60
55
50
45
40
35
37
36
COM3
COM2
COM1
COM0
C1
C0
V3
VCC
VSS
V2
V1
P47 (KEY7)
P46 (KEY6)
P45 (KEY5)
P44 (KEY4)
P43 (TO6/KEY3)
P42 (TI6/KEY2)
P41 (TO4/KEY1)
P40 (TI4/KEY0)
P85
P84 ( WAIT )
P83 (TO3)
P82 (TI2)
P81 (RXD1)
P80 (TXD1)
P77 ( NMI )
P76 (TOA)
P75 (TIB/INTB)
VSS
P74 (TIA/INTA)
P73 (SCOUT)
P72 (TO8)
P71 (TI9/INT9)
P70 (TI8/INT8)
P67 (TO1)
P66 (TI0/INT7)
Figure 2.1.1 Pin Assignment (144-pin LQFP)
93PW20A-4
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TMP93PW20A
2.2 Pin Names and Functions
The TMP93PW20A has MCU mode and PROM mode.
(1) Pin functions of TMP93PW20A in MCU mode.
Pin Names
P00 to P07
AD0 to AD7
P10 to P17
AD8 to AD15
A8 to A15
P20 to P27
A0 to A7
A16 to A23
P30
RD
P31
WR
P32
HWR
P33
INT0
P34
INT1
P35
INT2
P36
INT3
P37
INT4
ADTRG
P40
TI4
KEY0
P41
TO4
KEY1
P42
TI6
KEY2
P43
TO6
KEY3
P44 to P47
KEY4 to KEY7
P50 to P57
AN0 to AN7
Table 2.2.1 Name and Function in MCU Mode (1/3)
Number
of Pins
I/O
Functions
8 I/O Port 0: I/O port that allows I/O to be selected at the bit level.
I/O Address and data (lower): Bits 0 to 7 for address and data bus.
8 I/O Port 1: I/O port that allows I/O to be selected at the bit level.
I/O Address and data (Upper): Bits 8 to 15 for address and data bus.
Output
Address: Bits 8 to 15 for address bus.
8 I/O Port 2: I/O port that allows I/O to be selected at the bit level (with pull-up resistor).
Output
Address: Bits 0 to 7 for address bus.
Output
Address: Bits 16 to 23 for address bus.
1
Output
Port 30: Output port.
Output
Read: Strobe signal for reading external memory.
(Read when reading internal memory at P3<P30> = 0, P3FC<P30F> = 1.)
1
Output
Port 31: Output port.
Output
Write: Strobe signal for writing data on pins AD0 to AD7.
1 I/O Port 32: I/O port (with pull-up resistor).
Output
High write: Strobe signal for writing data on pins AD8 to AD15.
1 I/O Port 33: I/O port (with pull-up resistor).
Input
Interrupt request pin 0: Interrupt request pin with programmable
level/rising/falling edge.
1 I/O Port 34: I/O port (with pull-up resistor).
Input
Interrupt request pin 1: Interrupt request pin with programmable rising/falling
edge.
1 I/O Port 35: I/O port (with pull-up resistor).
Input
Interrupt request pin 2: Interrupt request pin with programmable rising/falling
edge.
1 I/O Port 36: I/O port (with pull-up resistor).
Input
Interrupt request pin 3: Interrupt request pin with programmable rising/falling
edge.
1 I/O Port 37: I/O port (with pull-up resistor).
Input
Interrupt request pin 4: Interrupt request pin with programmable rising/falling
edge.
Input
ADTRG Input AD external trigger pin: External trigger pin to start AD conversion.
1 I/O Port 40: I/O port (with pull-up resistor).
Input
Timer input 4: 16-bit timer 4 input.
Input
Key input 0: Key-on wakeup pin 0.
1 I/O Port 41: I/O port (with pull-up resistor).
Output
Timer output 4: 16-bit timer 4 output.
Input
Key input 1: Key-on wakeup pin 1.
1 I/O Port 42: I/O port (with pull-up resistor).
Input
Timer input 6: 16-bit timer 6 input.
Input
Key input 2: Key-on wakeup pin 2.
1 I/O Port 43: I/O port (with pull-up resistor).
Output
Timer output 6: 16-bit timer 6 output.
Input
Key input 3: Key-on wakeup pin 3.
4 I/O Port 44 to 47: I/O port (with pull-up resistor).
Input
Key input 4 to 7: Key-on wakeup pin 4 to 7.
8
Input
Port 50 to 57: Pin used to input port.
Input
Analog input 0 to 7.
93PW20A-5
2004-02-10