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NB3N853501E
3.3 V LVTTL/LVCMOS 2:1
MUX to 4 LVPECL
Differential Clock Fanout
Buffer Outputs with Clock
Enable and Clock Select
Description
The NB3N853501E is a pure 3.3 V supply 2:1:4 clock distribution
fanout buffer. Input MUX selects one of two LVCMOS/LVTTL CLK
lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using
LVCMOS/LVTTL levels. Outputs are LVPECL levels and are
synchronously enabled by CLK_EN using LVCMOS/LVTTL levels
(HIGH to enable outputs, LOW to disable output).
Features
Four differential LVPECL Outputs
Two Selectable LVCMOS/LVTTL CLOCK Inputs
Up to 266 MHz Clock Operation
Output to Output Skew: 30 ps (Max.)
Device to Device Skew 250 ps (Max.)
Propagation Delay 2.0 ns (Max.)
Operating range: VCC = 3.3 ±5% V( 3.135 to 3.465 V)
Additive Phase Jitter, RMS: 62 fs (Typ)
Synchronous Clock Enable Control
Industrial Temp. Range (40°C to 85°C)
PbFree TSSOP20 Package
These are PbFree Devices
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MARKING
DIAGRAM
TSSOP20
DT SUFFIX
CASE 948E
NB3N
501E
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2011
November, 2011 Rev. 2
1
Publication Order Number:
NB3N853501E/D

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NB3N853501E
VEE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
VCC
1
2
3
4
5
6
7
8
9
10
20 Q0
19 Q0
18 VCC
17 Q1
16 Q1
15 Q2
14 Q2
13 VCC
12 Q3
11 Q3
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Number
1
2
Name
VEE
CLK_EN
3 CLK_SEL
4 CLK0
5, 6, 8, 9
6
nc
CLK1
10, 13, 18
11, 14, 16,
19
12, 15, 16,
20
VCC
Q[3:0]
Q[3:0]
I/O
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVPECL
LVPECL
Open
Default
Pullup
Pulldown
Description
Negative (Ground) Power Supply pin must be externally connected to
power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
Clock Input Select (HIGH selects CLK1, LOW selects CLK0 input)
Pulldown Clock 0 Input. Float open when unused.
Pulldown
No Connect
Clock 1 Input. Float open when unused.
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Invert Differential Outputs
True Differential Outputs
Table 2. FUNCTIONS
Inputs
Outputs
CLK_EN
CLK_SEL
Input Function
Output Function
Qx Qx
0 0 CLK0 input selected
Disabled
LOW
HIGH
0 1 CLK1 Input Selected
Disabled
LOW
HIGH
1 0 CLK0 input selected
Enabled
CLK0
Invert of
CLK1
1 1 CLK1 Input Selected
Enabled
CLK1
Invert of
CLK1
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
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NB3N853501E
Figure 3. CLK_EN TIMING DIAGRAM
Table 3. ATTRIBUTES (Note 2)
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
50 kW
50 kW
> 2 kV
> 200 V
Level 1
UL 94 V0 @ 0.125 in
28 to 34
317 Devices
Table 4. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
Condition 1 Condition 2
Rating
Unit
VCC Supply Voltage
Vin Input Voltage
Cin Input Capacitance
Iout Output Current
Continuous
Surge
4.6
0.5 v VI v VCC + 0.5
4
50
100
V
V
pF
mA
TA Operating Temperature Range, Industrial
Tstg Storage Temperature Range
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
TSSOP20
40 to v +85
65 to +150
140
50
°C
°C
°C/W
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
SingleLayer
PCB (700 mm2,
2 oz)
128
°C/W
200 lfpm
MultiLayer
PCB (700 mm2,
2 oz)
94
qJC Thermal Resistance (JunctiontoCase)
(Note 4)
TSSOP20
23 to 41
°C/W
Tsol Wave Solder
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board 2S2P (2 signal, 2 power).
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NB3N853501E
Table 5. DC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), GND = 0 V, TA = 40°C to +85°C (Note 5)
Symbol
Characteristic
Min Typ Max
Unit
IEE Power Supply Current
VIH Input HIGH Voltage
50 mA
2
VCC +
V
0.3
VIL Input LOW Voltage
CLK0 CLK1
CLK_EN CLK_SEL
0.3
0.3
1.3 V
0.8
IIH Input High Current (VCC = Vin = 3.456 V)
CLKx, CLK_SEL
CLK_EN
150 mA
5
IIL
Input LOW Current (VCC = 3.456 V; Vin = GND)
CLKx, CLK_SEL
CLK_EN
5
150
mA
VOH Output HIGH Voltage
VCC
1.4
VCC
0.9
V
VOL Output LOW Voltage
VCC
2.0
VCC
1.7
V
VOUTSWING Output Voltage Swing (peaktopeak)
0.6 1.0 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs terminated 50 W to VCC 2.0 V, see Figure 4. Input levels of 0.8 V and 2.4 V unless stated otherwise.
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NB3N853501E
Table 6. AC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), GND = 0 V, TA = 40°C to +85°C (Note 6)
Symbol
Characteristic
Min Typ Max
Unit
FMAX
tPD
tSKEWDC
tSKEWOO
tSKEWDD
tJIT
Maximum Operating Frequency
Propagation Delay
Duty Cycle Skew same path similar conditions at 50 MHz
Output to Output Skew Within A Device
DevicetoDevice Skew similar path and conditions
Additive Phase Noise Jitter (RMS) @ 155.52 MHz (Integrated from 12 kHz to
20 MHz) See Figure 6.
0 266 MHz
0.9 2.0 ns
48 50 52 %
30 ps
250 ps
0.062
ps
tr/tf Output rise and fall times @ 266 MHz (20% and 80% points)
240 700 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to VCC 2.0 V, see Figure 4. Input levels of 0.8 V and 2.4 V unless stated otherwise. Measured from Input Midpoint
(VDD/2) to differential Output crosspoints, see Figure 5.
Figure 4. Typical Test Setup and Termination for Evaluation. The VCC of 2.0 V and VEE of 1.3 ±0.165 V Split
supply allows a direct connection to an oscilloscope 50 W impedance input module. Also reference AND8020.
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