CL12464FF.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 CL12464FF 데이타시트 다운로드

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CL12464FF
LVDS Receiver 24bit FPD-link 85MHz
Introduction
The CL12464FF receiver converts serial four LVDS data streams data back into parallel 28bits (24bits of
RGB data and 4bits of HSYNC, VSYNC, DE and Control1) of LVCMOS parallel. The CL12464FF
receiver’ outputs are Falling edge clock. The CL12464FF receiver is an ideal means to solve EMI and cable
size problems associated with wide, high-speed LVCMOS interfaces.
Feature
Input Clock: 20MHz~85MHz Input Data Rate: 140Mbps~595Mbps
Output Clock: 20MHz to 85MHz shift clock support
Low power single 3.3V
A falling edge strobe
Supports VGA, SVGA, XGA, SXGA, SXGA+
Narrow bus reduces cable size
PLL requires no external components
Power down mode
Low Profile 56 Lead TSSOP Package
345mV swing LVDS devices for low EMI
Supports Fail-Safe function to all input channels
Pin Compatible with DS90C384/386, THC63LVDM84B
Block Diagram
CURIOUS Corporation
1
Rev. 1.00

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CL12464FF
Pin Configuration
1
RxOUT22
2
RxOUT23
3
RxOUT24
GND
4
5
RxOUT25
6
RxOUT26
7
RxOUT27
8
LVDS GND
RxIN0
9
RxIN0
10
RxIN1
11
RxIN1
12
13
LVDS Vcc
14
LVDS GND
RxIN2
15
RxIN2
16
17
RxCLKIN
18
RxCLKIN
RxIN3
19
RxIN3
20
21
LVDS GND
22
PLL GND
PLL Vcc
23
24
PLL GND
25
Power Down
26
RxCLKOUT
RxOUT0
27
GND
28
LVDS Receiver 24bit FPD-link 85MHz
56 Vcc
55 RxOUT21
54 RxOUT20
53 RxOUT19
52 GND
51 RxOUT18
50 RxOUT17
49 RxOUT16
48 Vcc
47 RxOUT15
46 RxOUT14
45 RxOUT13
44 GND
43 RxOUT12
42 RxOUT11
41 RxOUT10
40 Vcc
39 RxOUT9
38 RxOUT8
37 RxOUT7
36 GND
35 RxOUT6
34 RxOUT5
33 RxOUT4
32 RxOUT3
31 Vcc
30 RxOUT2
29 RxOUT1
CURIOUS Corporation
2
Rev. 1.00

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CL12464FF
Pin Description
Pin Name
RxOUT
RxIN+
RxIN-
RxCLKOUT
RxCLKIN+
RxCLKIN-
Power Down
Vcc / GND
PLL Vcc / PLL GND
LVDS Vcc / LVDS GND
LVDS Receiver 24bit FPD-link 85MHz
No of Pin
28
4
4
1
1
1
1
3/5
1/2
2/4
I/O
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
Pin Description
LVCMOS Data Outputs
Positive LVDS Differential Data Inputs
Negative LVDS Differential Data Inputs
LVCMOS Level Clock Output
Positive LVDS Differential Clock Input
Negative LVDS Differential Clock Input
H:Normal Operation
L:Power Down (all Outputs are Hi-Z)
Power Supply/Ground Pins for LVCMOS Outputs
Power Supply/Ground Pins for PLL
Power Supply/Ground Pins for LVDS Inputs
Control Signal Truth Table
Power Down
0
0
0
0
1
1
1
1
R_F
0
0
1
1
0
0
1
1
OE
0
1
0
1
0
1
0
1
RxOUT
All Outputs Hi-Z
All ”0” Outputs
All Outputs Hi-Z
All ”0” Outputs
All Outputs Hi-Z
All Data Outputs
All Outputs Hi-Z
All Data Outputs
RxCLKOUT
Output Hi-Z
”0” Output
Output Hi-Z
”0” Output
Output Hi-Z
Falling Edge
Output Hi-Z
Rising Edge
CURIOUS Corporation
3
Rev. 1.00

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CL12464FF
Absolute Maximum Ratings
Supply Voltages
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4sec)
Maximum Power Dissipation Capacity at 25
LVDS Receiver 24bit FPD-link 85MHz
-0.3V to +4V
-0.3V to (Vcc+0.3V)
-0.3V to (Vcc+0.3V)
-0.3V to (Vcc+0.3V)
+150
-65 to +150
+260
1.4 W
Electrical Characteristics
1. LVCMOS DC Specification
Symbol
Parameter
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIN Input Current
VOH High Level Output Voltage
VOL Low Level Output Voltage
Vcc=3.0V to 3.6V Ta=-10to 70
Conditions
min typ max unit
2.0
GND
VCC V
0.8
VIN=VCC,GND,2.5V or 0.4V
±5.1 ±10 μA
IOH=-0.4mA
IOL=12mA
2.4
0.8 V
2. LVDS DC Specification
Symbol
Parameter
VTH Differential Input High Threshold
VTL Differential Input Low Threshold
IIN Input Current
Vcc=3.0V to 3.6V Ta=-10to 70
Conditions
min typ max unit
VCM=+1.2V
-100
100 mV
0VVINVCC
±10 μA
3. Receiver Supply Current
Vcc=3.0V to 3.6V Ta=-10to 70
Symbol
Parameter
Conditions
min typ max unit
ICCRW
ICCRG
Receiver
Supply Current
CL=8pF
Worst Case Pattern
CL=5pF
16Gray Scale Pattern
f=65MHz
f=85MHz
f=65MHz
f=85MHz
73 94
83
40
96
54
mA
52 64
ICCRZ
Power Down=Low
10 μA
CURIOUS Corporation
4
Rev. 1.00

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CL12464FF
4. Switching Characteristics
Symbol
Parameter
RCOP RxCLK OUT Period
RCOH RxCLK OUT High Time
RCOL RxCLK OUT Low Time
CLHT LVCMOS Low to High Transition Time
CHLT LVCMOS High to Low Transition Time
RSPOS0
RSPOS1
RSPOS2
RSPOS3
RSPOS4
RSPOS5
RSPOS6
RSRC
Receiver Input Strobe Position for Bit 0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxOUT Setup to RxCLK OUT
RHRC RxOUT Hold to RxCLK OUT
RCCD RxCLK IN to RxCLK OUT Delay
RPLLS Receiver Phase Lock Loop Set
RPDD Receiver Power Down Delay
LVDS Receiver 24bit FPD-link 85MHz
Vcc=3.0V to 3.6V Ta=-10to 70
min typ max unit
7.41 T
50
T/2
T/2 ns
13
13
-0.5 0 +0.5
T/7-0.5 T/7 T/7+0.5
2T/7-0.5 2T/7 2T/7+0.5
3T/7-0.5 3T/7 3T/7+0.5 ns
4T/7-0.5 4T/7 4T/7+0.5
5T/7-0.5 5T/7 5T/7+0.5
6T/7-0.5 6T/7 6T/7+0.5
T/2-2.5
T/2-2.5
ns
4T/7
10 ms
1 us
Fail-Safe Function
The CL12464FF receiver output ”high” when the differential inputs is :
1) Open
2) Undriven and Shorted
3) Undriven and Terminated
CURIOUS Corporation
5
Rev. 1.00