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SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
256Mb E-die SDRAM Specification
54pin sTSOP-II
Revision 1.0
August. 2003
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 August, 2003

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SDRAM 256Mb E-die (x4, x8, x16)
Revision History
Revision 1.0 (August. 2003)
- First release.
CMOS SDRAM
Rev. 1.0 August, 2003

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SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchro-
nous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of oper-
ating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S560432E-NC(L)75
K4S560832E-NC(L)75
K4S561632E-NC(L)60/75
Orgainization
64M x 4
32M x 8
16M x 16
Max Freq.
133MHz
133MHz
166/133MHz
Interface
LVTTL
LVTTL
LVTTL
Package
54pin sTSOP
54pin sTSOP
54pin sTSOP
Organization
64Mx4
32Mx8
16Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
A0-A8
Row & Column address configuration
Rev. 1.0 August, 2003

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SDRAM 256Mb E-die (x4, x8, x16)
Package Physical Dimension
54pin sTSOP(II)-300
#54
(1.00)
#28
(2.00 Dp0~0.05 BTM)
#1 #27
(2-R 0.15)
(0.50)
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASSY OUT QUALITY
14.40MAX
(14.20)
14.00±0.10
(14°)
0.50TYP
0.50±0.05
[ 0.07 MAX ]
0.20
+0.075
-0.035
(14°)
CMOS SDRAM
Units : Millimeters
(2-R 0.15)
(2-R 0.30)
(14°)
0.125
+0.075
-0.035
0.10 MAX
0.25TYP
0×~8×
Rev. 1.0 August, 2003

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SDRAM 256Mb E-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
Data Input Register
CLK
ADD
Bank Select
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 August, 2003