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ADVANCED
LINEAR
DEVICES, INC.
ALD1712A/ALD1712B
ALD1712
RAIL-TO-RAIL PRECISION OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
The ALD1712A/ALD1712B/ALD1712 is a monolithic precision opera-
tional amplifier intended primarily for a wide range of analog applications
in +5V single power supply and ±5V dual power supply systems as well
as +5V to +10V battery operated systems. All device characteristics are
specified for +5V single supply or ±2.5V dual supply systems. It is
manufactured with Advanced Linear Devices' enhanced ACMOS silicon
gate CMOS process and is available as a standard cell in ALD's ASIC
"Function-Specific" library.
The ALD1712A/ALD1712B/ALD1712 has an input stage that operates to
+300mV above and -300mV below the supply voltages with no adverse
effects and/or phase reversals. It has been developed specifically with
the 5V single supply or ±2.5V dual supply user in mind.
Several important characteristics of the device make many applications
easy to implement for these supply voltages. First, the operational
amplifier can operate with rail-to-rail input and output voltages. This
feature allows numerous analog serial stages to be implemented without
losing operating voltage margin. Second, the device was designed to
accommodate mixed applications where digital and analog circuits may
work off the same 5V power supply. Third, the output stage can drive up
to 400pF capacitive, and 1Kresistive loads in non-inverting unity gain
connection, and up to 4000pF at a gain of 5. These features, coupled with
extremely low input currents, high voltage gain, useful bandwidth of
1.5MHz, slew rate of 2.1V/µs, low power dissipation, low offset voltage
and temperature drift, make the ALD1712A/ALD1712B/ALD1712 a truly
versatile, user friendly, operational amplifier.
On-chip offset voltage trimming allows the device to be used without
nulling in most applications. The device offers typical offset drift of less
than 5µV/°C which eliminates many trim or temperature compensation
circuits. For precision applications, the ALD1712A/ALD1712B/ALD1712
is designed to settle to 0.01% in 8µs. The unique characteristics at input
and output are modeled in an available macromodel. Additionally, robust
design and rigorous screening make this device especially suitable for
operation in temperature-extreme environments and rugged conditions.
ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS))
Operating Temperature Range
0°C to +70°C
0°C to +70°C
-55°C to 125°C
8-Pin
Small Outline
Package (SOIC)
8-Pin
Plastic Dip
Package
8-Pin
CERDIP
Package
ALD1712ASAL
ALD1712BSAL
ALD1712SAL
ALD1712APAL
ALD1712BPAL
ALD1712PAL
ALD1712ADA
ALD1712BDA
ALD1712DA
* Contact factory for leaded (non-RoHS) or high temperature versions.
FEATURES
• Linear mode operation with input voltages
300mV beyond supply rails
• Symmetrical complementary output drive
• Output voltages to within 2mV of power
supply rails
• High load capacitance capability --
4000pF typical
• No frequency compensation required --
unity gain stable
• Extremely low input bias currents --
0.01pA typical
• Dual power supply ±2.5V to ±5.0V
• Single power supply +5V to +10V
• High voltage gain – typically 85V/mV
@ ±2.5V and 250V/mV @ ±5.0V
• Drive as low as 1Kload with 5mA
drive current
• Output short circuit protected
• Unity gain bandwidth of 1.5MHz
• Slew rate of 2.1V/µs
• Suitable for rugged, temperature-extreme
environments
APPLICATIONS
• Voltage amplifier
• Voltage follower/buffer
• Charge integrator
• Photodiode amplifier
• Data acquisition systems
• High performance portable instruments
• Signal conditioning circuits
• Sensor and transducer amplifiers
• Low leakage amplifiers
• Active filters
• Sample/Hold amplifier
• Picoammeter
• Current to voltage converter
• Coaxial cable driver
PIN CONFIGURATION
N/C 1
-IN 2
2
8 N/C
7 V+
+IN 3
6 OUT
V- 4
5 N/C
TOP VIEW
SAL, PAL, DA PACKAGES
* N/C pins are internally connected. Do not connect externally.
Rev 2.1 ©2010 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286
www.aldinc.com

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ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+
Differential input voltage range
Power dissipation
Operating temperature range SAL, PAL packages
DA package
Storage temperature range
Lead temperature, 10 seconds
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
10.6V
-0.3V to V+ +0.3V
600 mW
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25°C VS = ±2.5V unless otherwise specified
Parameter
Supply
Voltage
Symbol
VS
V+
1712A
Min Typ
±2.0
4.0
Max
±5.0
10.0
1712B
1712
Min Typ Max Min Typ
±2.0 ±5.0 ±2.0
4.0 10.0 4.0
Max
±5.0
10.0
Unit
V
V
Test Conditions
Dual Supply
Single Supply
Input Offset
Voltage
Input Offset
Current
Input Bias
Current
Input Voltage
Range
Input
Resistance
VOS
IOS
IB
VIR
RIN
0.05 0.15
0.35
0.1 0.25
0.55
0.25 0.5 mV
1.0 mV
0.01 10
280
0.01 10
280
0.01 10 pA
280 pA
0.01 10
280
0.01 10
280
0.01 10 pA
280 pA
-0.3
5.3 -0.3
5.3 -0.3
5.3 V
-2.8
+2.8 -2.8
+2.8 -2.8
+2.8 V
1013
1013
1013
RS 100K
0°C TA +70°C
TA = 25°C
0°C TA +70°C
TA = 25°C
0°C TA +70°C
V+ = +5; notes 2,5
VS = ±2.5V
Input Offset
Voltage Drift
TCVOS
5
Power Supply PSRR
Rejection Ratio
65 85
65 85
Common Mode CMRR
Rejection Ratio
65 83
65 83
5
65 85
65 85
65 83
65 83
5
63 85
63 85
63 83
63 83
µV/°C RS 100K
dB RS 100K
dB 0°C TA +70°C
dB RS 100K
dB 0°C TA +70°C
Large Signal
Voltage Gain
Output
Voltage
Range
Output Short
Circuit Current
AV 50 85
400
20
50 85
400
20
50 85
400
20
V/mV
V/mV
V/mV
RL = 10K
RL 1M
RL = 10K
0°C TA +70°C
VO low
VO high
VO low
VO high
0.002 0.01
0.002 0.01
0.002 0.01
4.99 4.998
4.99 4.998
4.99 4.998
-2.44 -2.35
-2.44 -2.35
-2.44 -2.35
2.35 2.44
2.35 2.44
2.35 2.44
V
V
V
V
RL = 1MV+ = +5V
0°C TA +70°C
RL = 10K
0°C TA +70°C
ISC 8 8 8 mA
Supply
Current
Power
Dissipation
Input
Capacitance
Bandwidth
Slew Rate
IS
PD
CIN
BW
SR
Rise time
Overshoot
Factor
tr
ALD1712A/ALD1712B
ALD1712
0.8 1.5
4.0 7.5
0.8 1.5
4.0 7.5
0.8 1.5 mA
VIN = 0V
No Load
4.0 7.5 mW VS = ±2.5V
1 1 1 pF
1.0 1.5
1.4 2.1
1.0 1.5
1.4 2.1
1.0 1.5
1.4 2.1
0.2 0.2 0.2
10 10 10
Advanced Linear Devices
MHz
V/µs
µs
%
AV = +1
RL = 10K
RL = 10K
RL = 10K
CL = 100pF
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OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
TA = 25°C VS = ±2.5V unless otherwise specified
Parameter
1712A
1712B
1712
Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Maximum Load
Capacitance
CL
400
4000
400
4000
400
4000
pF
pF
Test Conditions
Gain = 1
Gain = 5
Input Noise
Voltage
en
26
26 26 nV/Hz f =1KHz
Input Current
Noise
in
0.6
0.6 0.6 fA/Hz f =10Hz
Settling
Time
ts
8.0
3.0
8.0 8.0 µs 0.01%
3.0 3.0 µs 0.1% AV = -1
RL = 5KCL= 50pF
TA = 25°C VS = ±5.0V unless otherwise specified
Parameter
1712A
1712B
1712
Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Power Supply
Rejection Ratio
PSRR
83
83 83 dB
Common Mode
Rejection Ratio
Large Signal
Voltage Gain
Output Voltage
Range
Bandwidth
Slew Rate
CMRR
83
83 83 dB
AV 250
250 250 V/mV
VO low
-4.90 -4.80
-4.90 -4.80
-4.90
VO high 4.80 4.93
4.80 4.93
4.80 4.93
BW 1.7
1.7 1.7
SR 2.8
2.8 2.8
-4.80 V
MHz
V/µs
Test Conditions
RS 100K
RS 100K
RL = 10K
RL = 10K
AV =+1
CL =50pF
VS = ±2.50V -55°C TA +125°C unless otherwise specified
Parameter
Input Offset
Voltage
Symbol
VOS
1712ADA
Min Typ Max
0.5 1.0
1712BDA
Min Typ Max Min
0.8 1.5
1712DA
Typ Max
1.2 2.5
Unit
mV
Input Offset
Current
Input Bias
Current
Power Supply
Rejection Ratio
Common Mode
Rejection Ratio
IOS
IB
PSRR
CMRR
4.0 4.0
4.0 4.0
60 83
60 83
60 83
60 83
60 83
60 83
4.0 nA
4.0 nA
dB
dB
Large Signal
Voltage Gain
Output Voltage
Range
AV 10 25
VO low
0.1
VO high 4.8 4.9
10 25
10 25
0.2 0.1
4.8 4.9
0.2 0.1
4.8 4.9
V/mV
0.2 V
V
Test Conditions
RS 100K
RS 100K
RS 100K
RL = 10K
RL 10K
RL 10K
ALD1712A/ALD1712B
ALD1712
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Design & Operating Notes:
1. The ALD1712A/ALD1712B/ALD1712 CMOS operational amplifier uses
a 3 gain stage architecture and an improved frequency compensation
scheme to achieve large voltage gain, high output driving capability,
and better frequency stability. In a conventional CMOS operational
amplifier design, compensation is achieved with a pole splitting capaci-
tor together with a nulling resistor. This method is, however, very bias
dependent and thus cannot accommodate the large range of supply
voltage operation as is required from a stand alone CMOS operational
amplifier. The ALD1712A/ALD1712B/ALD1712 is internally compen-
sated for unity gain stability using a novel scheme that does not use a
nulling resistor. This scheme produces a clean single pole roll off in the
gain characteristics while providing for more than 70 degrees of phase
margin at the unity gain frequency. A unity gain buffer using the
ALD1712A/ALD1712B/ALD1712 will typically drive 400pF of external
load capacitance without stability problems. In the inverting unity gain
configuration, it can drive up to 800pF of load capacitance. Compared
to other CMOS operational amplifiers, the ALD1712A/ALD1712B/
ALD1712 has shown itself to be more resistant to parasitic oscillations.
2. The ALD1712A/ALD1712B/ALD1712 has complementary p-channel
and n-channel input differential stages connected in parallel to accom-
plish rail to rail input common mode voltage range. This means that with
the ranges of common mode input voltage close to the power supplies,
one of the two differential stages is switched off internally. To maintain
compatibility with other operational amplifiers, this switching point has
been selected to be about 1.5V above the negative supply voltage.
Since offset voltage trimming on the ALD1712A/ALD1712B/ALD1712
is made when the input voltage is symmetrical to the supply voltages,
this internal switching does not affect a large variety of applications
such as an inverting amplifier or non-inverting amplifier with a gain
larger than 2.5 (5V operation), where the common mode voltage does
not make excursions below this switching point. The user should
however, be aware that this switching does take place if the operational
amplifier is connected as a unity gain buffer and should make provision
in his design to allow for input offset voltage variations.
3. The input bias and offset currents are essentially input protection diode
reverse bias leakage currents, and are typically less than 1pA at room
temperature. This low input bias current assures that the analog signal
from the source will not be distorted by input bias currents. Normally,
this extremely high input impedance of greater than 1012would not be
a problem as the source impedance would limit the node impedance.
However, for applications where source impedance is very high, it may
be necessary to limit noise and hum pickup through proper shielding.
4. The output stage consists of class AB complementary output drivers,
capable of driving a low resistance load. The output voltage swing is
limited by the drain to source on-resistance of the output transistors as
determined by the bias circuitry, and the value of the load resistor.
When connected in the voltage follower configuration, the oscillation
resistant feature, combined with the rail to rail input and output feature,
makes an effective analog signal buffer for medium to high source
impedance sensors, transducers, and other circuit networks.
5. The ALD1712A/ALD1712B/ALD1712 operational amplifier has been
designed to provide full static discharge protection. Internally, the
design has been carefully implemented to minimize latch up. However,
care must be exercised when handling the device to avoid strong static
fields that may degrade a diode junction, causing increased input
leakage currents. In using the operational amplifier, the user is advised
to power up the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages to not exceed 0.3V of the power
supply voltage levels.
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
±7
±6 TA = 25°C
±5
±4
±3
±2
±1
0
0 ±1
±2 ±3 ±4 ±5
SUPPLY VOLTAGE (V)
±6
±7
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
1000
} -55°C
} +25°C
100
} +125°C
10
1
0
RL= 10K
RL= 5K
±2 ±4 ±6
SUPPLY VOLTAGE (V)
±8
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
1000
100 VS = ±2.5V
10
1.0
0.1
0.01
-50
-25 0 25 50 75 100
AMBIENT TEMPERATURE (°C)
125
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
±5
INPUTS GROUNDED
±4 OUTPUT UNLOADED
±3
±2
±1
0
0
TA = -55ºC
-25°C
+25°C
+80°C
+125°C
±1 ±2 ±3
±4
SUPPLY VOLTAGE (V)
±5
±6
ALD1712A/ALD1712B
ALD1712
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TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
OUTPUT VOLTAGE SWING AS A
FUNCTION OF SUPPLY VOLTAGE
±7
±6 -55°C TA 125°C
±5 RL = 10K
RL = 10K
±4 RL = 2K
±3
±2
0
±1
±2 ±3 ±4
±5
SUPPLY VOLTAGE (V)
±6 ±7
INPUT OFFSET VOLTAGE AS A FUNCTION
OF AMBIENT TEMPERATURE
REPRESENTATIVE UNITS
+5
+4 VS = ±2.5V
+3
+2
+1
0
-1
-2
-3
-4
-5
-50 -25 0 +25 +50 +75 +100 +125
AMBIENT TEMPERATURE (°C)
1000
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
100
VS = ±2.5V
10 TA = 25°C
1
1K
10K 100K
LOAD RESISTANCE ()
1000K
LARGE - SIGNAL TRANSIENT
RESPONSE
5V/div
VS = ±2.5V
TA = 25°C
RL = 10K
CL = 50pF
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF FREQUENCY
120
100
80
VS = ±2.5V
TA = 25°C
60 0
40 45
20 90
0
-20
1
135
180
10 100 1K 10K 100K 1M 10M
FREQUENCY (Hz)
INPUT OFFSET VOLTAGE AS A FUNCTION
OF COMMON MODE INPUT VOLTAGE
6
4 VS = ±2.5V
TA = 25°C
2
0
-2
-4
-6
-2 -1 0 +1 +2 +3
COMMON MODE INPUT VOLTAGE (V)
VOLTAGE NOISE DENSITY AS A
FUNCTION OF FREQUENCY
150
125
100
VS = ±2.5V
TA = 25°C
75
50
25
0
10
100 1K 10K 100K
FREQUENCY (Hz)
SMALL - SIGNAL TRANSIENT
RESPONSE
1000K
100mV/div
VS = ±2.5V
TA = 25°C
RL = 10K
CL = 50pF
1V/div
2µs/div
20mV/div
2µs/div
ALD1712A/ALD1712B
ALD1712
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