LTC2377-16.pdf 데이터시트 (총 24 페이지) - 파일 다운로드 LTC2377-16 데이타시트 다운로드

No Preview Available !

Features
n 500ksps Throughput Rate
n ±0.5LSB INL (Max)
n Guaranteed 16-Bit No Missing Codes
n Low Power: 6.8mW at 500ksps, 6.8µW at 500sps
n 97dB SNR (Typ) at fIN = 2kHz
n123dB THD (Typ) at fIN = 2kHz
n Digital Gain Compression (DGC)
n Guaranteed Operation to 125°C
n 2.5V Supply
n Fully Differential Input Range ±VREF
n VREF Input Range from 2.5V to 5.1V
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-Lead MSOP and 4mm × 3mm DFN Packages
Applications
n Medical Imaging
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n Industrial Process Control
n Low Power Battery-Operated Instrumentation
n ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
LTC2377-16
16-Bit, 500ksps, Low Power
SAR ADC with 97dB SNR
Description
The LTC®2377-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2377-16 has a
±VREF fully differential input range with VREF ranging from
2.5V to 5.1V. The LTC2377-16 consumes only 6.8mW and
achieves ±0.5LSB INL maximum, no missing codes at 16
bits with 97dB SNR.
The LTC2377-16 has a high speed SPI-compatible se-
rial interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 500ksps
throughput with no cycle latency makes the LTC2377-16
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing exter-
nal timing considerations. The LTC2377-16 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
The LTC2377-16 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
Typical Application
2.5V 1.8V TO 5V
10µF
0.1µF
VREF
0V
VREF
0V
+
20Ω
6800pF
VDD OVDD CHAIN
IN+
RDL/SDI
SDO
3300pF
LTC2377-16
SCK
20Ω
IN
6800pF
REF
BUSY
CNV
GND REF/DGC
2.5V TO 5.1V
237716 TA01
47µF
(X5R, 0805 SIZE)
SAMPLE CLOCK
VREF
32k Point FFT fS = 500ksps, fIN = 2kHz
0 SNR = 97.2dB
–20 THD = –123dB
SINAD = 97.2dB
–40 SFDR = 126dB
–60
–80
–100
–120
–140
–160
–180
0
50 100 150 200 250
FREQUENCY (kHz)
237716 TA02
237716f
1

No Preview Available !

LTC2377-16
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VDD)................................................2.8V
Supply Voltage (OVDD).................................................6V
Reference Input (REF)..................................................6V
Analog Input Voltage (Note 3)
IN+, IN.......................... (GND –0.3V) to (REF + 0.3V)
REF/DGC Input (Note 3)..... (GND –0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3)............................ (GND –0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)............................ (GND –0.3V) to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2377C................................................. 0°C to 70°C
LTC2377I..............................................–40°C to 85°C
LTC2377H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
CHAIN
VDD
GND
IN+
IN
GND
REF
REF/DGC
1
2
3
4
5
6
7
8
TOP VIEW
17
GND
16 GND
15 OVDD
14 SDO
13 SCK
12 RDL/SDI
11 BUSY
10 GND
9 CNV
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
CHAIN 1
GVIINDNNDD+–
2
3
4
5
GND 6
REF 7
REF/DGC 8
16 GND
15
14
SODVDOD
13 SCK
12 RDL/SDI
11 BUSY
10 GND
9 CNV
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2377CMS-16#PBF
LTC2377CMS-16#TRPBF 237716
16-Lead Plastic MSOP
0°C to 70°C
LTC2377IMS-16#PBF
LTC2377IMS-16#TRPBF 237716
16-Lead Plastic MSOP
–40°C to 85°C
LTC2377HMS-16#PBF
LTC2377HMS-16#TRPBF 237716
16-Lead Plastic MSOP
–40°C to 125°C
LTC2377CDE-16#PBF
LTC2377IDE-16#PBF
LTC2377CDE-16#TRPBF 23776
LTC2377IDE-16#TRPBF 23776
16-Lead (4mm × 3mm) Plastic DFN
16-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
237716f
2

No Preview Available !

LTC2377-16
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
VIN+
VIN
VIN+ – VIN
VCM
Absolute Input Range (IN+)
Absolute Input Range (IN)
Input Differential Voltage Range
Common-Mode Input Range
(Note 5)
(Note 5)
VIN = VIN+ – VIN
l –0.05
l –0.05
l –VREF
l VREF/2–
0.1
VREF/2
VREF + 0.05
VREF + 0.05
+VREF
VREF/2+
0.1
V
V
V
V
IIN Analog Input Leakage Current
CIN Analog Input Capacitance
Sample Mode
Hold Mode
l ±1 µA
45 pF
5 pF
CMRR
Input Common Mode Rejection Ratio
fIN = 250kHz
86 dB
C onverter Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Resolution
l 16
Bits
No Missing Codes
l 16
Bits
Transition Noise
INL Integral Linearity Error
(Note 6)
l –0.5
0.15
±0.2
LSBRMS
0.5 LSB
DNL Differential Linearity Error
l –0.5 ±0.1
0.5
LSB
BZE Bipolar Zero-Scale Error
(Note 7)
l –4
0
4
LSB
Bipolar Zero-Scale Error Drift
1 mLSB/°C
FSE Bipolar Full-Scale Error
(Note 7)
l –13
±2
13
LSB
Bipolar Full-Scale Error Drift
±0.05
ppm/°C
Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
fIN = 2kHz, VREF = 5V
l 94.6
97
fIN = 2kHz, VREF = 5V, (H-Grade)
l 94.5
97
fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 5V, REF/DGC = GND
fIN = 2kHz, VREF = 2.5V
l 95.3
l 94.5
l 92.1
97
96.4
95
fIN = 2kHz, VREF = 5V, (H-Grade)
l 95.2
fIN = 2kHz, VREF = 5V, REF/DGC = GND, (H-Grade) l 94.3
fIN = 2kHz, VREF = 2.5V, (H-Grade)
l 91.8
97
96.4
95
fIN = 2kHz, VREF = 5V
l –123 –103
ffIINN
=
=
2kHz,
2kHz,
VVRREEFF
=
=
5V, REF/DGC
2.5V
=
GND
l
l
–125 –101
–122 –103
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
SFDR
Spurious Free Dynamic Range
–3dB Input Bandwidth
fIN = 2kHz, VREF = 5V
l 104
124
34
dB
MHz
Aperture Delay
500 ps
Aperture Jitter
4 ps
Transient Response
Full-Scale Step
1.46 µs
237716f
3

No Preview Available !

LTC2377-16
Reference Input The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
VREF
IREF
VIHDGC
VILDGC
Reference Voltage
Reference Input Current
High Level Input Voltage REF/DGC Pin
Low Level Input Voltage REF/DGC Pin
(Note 5)
(Note 9)
l 2.5
l
l 0.8VREF
l
0.32
5.1
0.4
0.2VREF
V
mA
V
V
D igital Inputs and Digital Outputs The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIN Digital Input Current
CIN Digital Input Capacitance
VOH High Level Output Voltage
VIN = 0V to OVDD
IO = –500µA
l 0.8 • OVDD
l
l –10
0.2 • OVDD
10
5
l OVDD – 0.2
V
V
µA
pF
V
VOL
IOZ
ISOURCE
ISINK
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
IO = 500µA
VOUT = 0V to OVDD
VOUT = 0V
VOUT = OVDD
l 0.2
l –10
10
–10
10
V
µA
mA
mA
Power Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
VDD
OVDD
IVDD
IOVDD
IPD
IPD
PD
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Power Down Mode
Power Down Mode
Power Dissipation
Power Down Mode
Power Down Mode
500ksps Sample Rate
500ksps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF)
Conversion Done (IVDD + IOVDD + IREF, H-Grade)
500ksps Sample Rate
Conversion
Conversion
Done
Done
((IIVVDDDD
+
+
IIOOVVDDDD
+
+
IIRREEFF),
H-Grade)
l
l
l
l
l
2.375
1.71
2.5
2.7
0.1
0.9
0.9
6.75
2.25
2.25
2.625
5.25
3.2
90
140
8
225
315
V
V
mA
mA
µA
µA
mW
µW
µW
A DC Timing Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
fSMPL
tCONV
tACQ
tHOLD
tCYC
tCNVH
tBUSYLH
tCNVL
tQUIET
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Maximum Time Between Acquisitions
Time Between Conversions
CNV High Time
CNVto BUSY Delay
Minimum Low Time for CNV
SCK Quiet Time from CNV
tACQ = tCYC – tHOLD (Note 10)
CL = 20pF
(Note 11)
(Note 10)
l
l1
l 1.46
l
l2
l 20
l
l 20
l 20
500 ksps
1.5 µs
µs
540 ns
µs
ns
13 ns
ns
ns
237716f
4

No Preview Available !

LTC2377-16
A DC timing characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
tSCK
tSCKH
tSCKL
tSSDISCK
tHSDISCK
tSCKCH
SCK Period
SCK High Time
SCK Low Time
SDI Setup Time From SCK
SDI Hold Time From SCK
SCK Period in Chain Mode
(Notes 11, 12)
(Note 11)
(Note 11)
tSCKCH = tSSDISCK + tDSDO (Note 11)
l 10
l4
l4
l4
l1
l 13.5
ns
ns
ns
ns
ns
ns
tDSDO
tHSDO
SDO Data Valid Delay from SCK
SDO Data Remains Valid Delay from SCK
CL = 20pF (Note 11)
CL = 20pF (Note 10)
l
l1
9.5 ns
ns
tDSDOBUSYL
tEN
tDIS
SDO Data Valid Delay from BUSY
Bus Enable Time After RDL
Bus Relinquish Time After RDL
CL = 20pF (Note 10)
(Note 11)
(Note 11)
l
l
l
5 ns
16 ns
13 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 500kHz,
REF/DGC = VREF.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000 and
1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS
or +FS untrimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9: fSMPL = 500kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
0.2*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
50%
tWIDTH
Figure 1. Voltage Levels for Timing Specifications
50%
237716 F01
237716f
5