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TH58NVG5S0FTAK0
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
32 GBIT (4G × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TH58NVG5S0F is a single 3.3V 32 Gbit (36,305,895,424 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 232) bytes × 64 pages × 16384 blocks.
The device has two 4328-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 4328-byte increments. The Erase operation is implemented in a single block
unit (256 Kbytes + 14.5 Kbytes: 4328 bytes × 64 pages).
The TH58NVG5S0F is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
x8
Memory cell array 4328 × 256K × 8 × 4
Register
4328 × 8
Page size
4328 bytes
Block size
(256K + 14.5K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 16064 blocks
Max 16384 blocks
Power supply
VCC = 2.7V to 3.6V
Access time
Cell array to register 30 µs max
Serial Read Cycle 25 ns min (CL=100pF)
Program/Erase time
Auto Page Program
Auto Block Erase
300 µs/page typ.
3 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
200 µA max
Package
TSOP I 48-P-1220-0.50C
4bit ECC for each 512Byte is required.
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PIN ASSIGNMENT (TOP VIEW)
PINNAMES
×8
NC
NC
NC
NC
NC
RY / BY 2
RY / BY 1
RE
CE 1
CE 2
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TH58NVG5S0FTAK0
I/O1 to I/O8
CE 1
CE 2
WE
RE
CLE
ALE
PSL
WP
RY/BY 1
RY/BY 2
VCC
VSS
I/O port
Chip enable (Chip A,B)
Chip enable (Chip C,D)
Write enable
Read enable
Command latch enable
Address latch enable
Power on select
Write protect
Ready/Busy (Chip A,B)
Ready/Busy (Chip C,D)
Power supply
Ground
TH58NVG5S0FTAK0
×8
48 NC
47 NC
46 NC
45 NC
44 I/O8
43 I/O7
42 I/O6
41 I/O5
40 NC
39 PSL
38 NC
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
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BLOCK DIAGRAM
I/O1
to
I/O8
CE 1
CLE
ALE
WE
RE
WP
PSL
RY / BY 1
CE 2
RY / BY 2
I/O
Control circuit
Logic control
RY / BY
I/O
Control circuit
Logic control
RY / BY
TH58NVG5S0FTAK0
(Chip A, B)
Status register
Address register
Command register
Control circuit
VCC VSS
Column buffer
Column decoder
Data register
Sense amp
Memory cell array
HV generator
Status register
Address register
Command register
Control circuit
Column buffer
Column decoder
Data register
Sense amp
Memory cell array
HV generator
(Chip C, D)
VCC VSS
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ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VCC
Power Supply Voltage
VIN Input Voltage
VI/O Input /Output Voltage
PD Power Dissipation
TSOLDER
Soldering Temperature (10 s)
TSTG
TOPR
Storage Temperature
Operating Temperature
TH58NVG5S0FTAK0
VALUE
0.6 to 4.6
0.6 to 4.6
0.6 to VCC + 0.3 (4.6 V)
0.3
260
55 to 150
-40 to 85
UNIT
V
V
V
W
°C
°C
°C
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMB0L
PARAMETER
CONDITION
CIN Input
VIN = 0 V
COUT
Output
VOUT = 0 V
* This parameter is periodically sampled and is not tested for every device.
MIN
MAX
40
40
UNIT
pF
pF
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TH58NVG5S0FTAK0
VALID BLOCKS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NVB Number of Valid Blocks
16064
16384
Blocks
NOTE:
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
VCC
Power Supply Voltage
2.7 3.6 V
VIH High Level input Voltage 2.7 V VCC 3.6 V
Vcc x 0.8
VCC + 0.3
V
VIL Low Level Input Voltage 2.7 V VCC 3.6 V
0.3*
Vcc x 0.2
* 2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta = -40 to 85, VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
CONDITION
IIL
ILO
ICCO0 *1
ICCO1 *2
ICCO2 *2
ICCO3 *2
ICCS
Input Leakage Current
Output Leakage Current
Power On Reset Current
Serial Read Current
Programming Current
Erasing Current
Standby Current
VIN = 0 V to VCC
VOUT = 0 V to VCC
PSL = GND or NU
PSL = VCC, FFh command input after
Power On
CE = VIL, IOUT = 0 mA, tcycle = 25 ns
CE = VCC 0.2 V, WP = 0 V/VCC,
PSL = 0 V/VCC/NU
MIN
TYP.
MAX
±10
±10
30
30
30
30
30
200
V
UNIT
µA
µA
mA
mA
mA
mA
µA
VOH
High Level Output Voltage IOH = −0.4 mA
2.4  
V
VOL Low Level Output Voltage IOL = 2.1 mA
  0.4 V
IOL
( RY / BY )
Output current of RY / BY
pin
VOL = 0.4 V
*1 Refer to application note (2) for detail
*2 Icco1/2/3 are the value of one chip, and an unselected chip is in Standby mode.
8
mA
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