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Data Sheet
14-Bit, 500 MSPS LVDS,
Dual Analog-to-Digital Converter
AD9684
FEATURES
Parallel LVDS (DDR) outputs
1.1 W total power per channel at 500 MSPS (default settings)
SFDR = 85 dBFS at 170 MHz fIN (500 MSPS)
SNR = 68.6 dBFS at 170 MHz fIN (500 MSPS)
ENOB = 10.9 bits at 170 MHz fIN
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −153 dBFS/Hz at 500 MSPS
1.25 V, 2.50 V, and 3.3 V supply operation
No missing codes
Internal analog-to-digital converter (ADC) voltage reference
Flexible input range and termination impedance
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
SYNC± input allows multichip synchronization
DDR LVDS (ANSI-644 levels) outputs
2 GHz usable analog input full power bandwidth
>96 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
Two integrated wideband digital processors per channel
12-bit numerically controlled oscillator (NCO)
3 cascaded half-band filters
Differential clock inputs
Serial port control
Integer clock divide by 2, 4, or 8
Small signal dither
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE
General-purpose software radios
Ultrawideband satellite receiver
Instrumentation (spectrum analyzers, network analyzers,
integrated RF test solutions)
Radar
Digital oscilloscopes
High speed data acquisition systems
DOCSIS CMTS upstream receiver paths
HFC digital reverse path receivers
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 DVDD DRVDD
(1.25V) (2.5V) (3.3V) (1.25V) (1.25V)
SPIVDD
(1.8V TO 3.4V)
BUFFER
VIN+A
VIN–A
ADC 14
CORE
FD_A
DIGITAL
DOWN-
CONVERTER
16
FD_B
BUFFER
VIN+B
VIN–B
V_1P0
CLK+
CLK–
ADC 14
CORE
DIGITAL
DOWN-
CONVERTER
CONTROL
REGISTERS
CLOCK
GENERATION
FAST
DETECT
SIGNAL MONITOR
SPI CONTROL
÷2
÷4
AD9684
÷8
D0±
D1±
D2±
D3±
D4±
D5±
D6±
D7±
D8±
D9±
D10±
D11±
D12±
D13±
DCO±
STATUS±
SYNC+
SYNC–
PDWN/
STBY
AGND DRGND
DGND SDIO SCLK CSB
Figure 1.
GENERAL DESCRIPTION
The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has
an on-chip buffer and a sample-and-hold circuit designed for
low power, small size, and ease of use. This product is designed
for sampling wide bandwidth analog signals. The AD9684 is
optimized for wide input bandwidth, a high sampling rate,
excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth buffered inputs, supporting a
variety of user selectable input ranges. An integrated voltage
reference eases design considerations. Each ADC data output is
internally connected to an optional decimate by 2 block.
The analog input and clock signals are differential inputs. Each
ADC data output is internally connected to two digital
downconverters (DDCs). Each DDC consists of four cascaded
signal processing stages: a 12-bit frequency translator (NCO),
and three half-band decimation filters supporting a divide by
factor of two, four, and eight.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9684
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings.......................................................... 16
Thermal Characteristics ............................................................ 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 19
Equivalent Circuits ......................................................................... 22
Theory of Operation ...................................................................... 24
ADC Architecture ...................................................................... 24
Analog Input Considerations.................................................... 24
Voltage Reference ....................................................................... 26
Clock Input Considerations ...................................................... 27
Power-Down/Standby Mode..................................................... 28
Temperature Diode .................................................................... 28
ADC Overrange and Fast Detect.................................................. 29
ADC Overrange.......................................................................... 29
Fast Threshold Detection (FD_A and FD_B) ........................ 29
Signal Monitor ................................................................................ 30
Digital Downconverters (DDCs).................................................. 31
DDC I/Q Input Selection .......................................................... 31
REVISION HISTORY
5/15—Revision 0: Initial Version
Data Sheet
DDC I/Q Output Selection ....................................................... 31
DDC General Description ........................................................ 31
Frequency Translation ................................................................... 37
General Description................................................................... 37
DDC NCO Plus Mixer Loss and SFDR................................... 38
Numerically Controlled Oscillator .......................................... 38
FIR Filters ........................................................................................ 40
General Description................................................................... 40
Half-Band Filters ........................................................................ 41
DDC Gain Stage ......................................................................... 42
DDC Complex to Real Conversion Block............................... 42
DDC Example Configurations ................................................. 43
Digital Outputs ............................................................................... 47
Digital Outputs ........................................................................... 47
ADC Overrange.......................................................................... 47
Multichip Synchronization............................................................ 48
SYNC± Setup and Hold Window Monitor............................. 49
Test Modes....................................................................................... 51
ADC Test Modes ........................................................................ 51
Serial Port Interface (SPI).............................................................. 52
Configuration Using the SPI..................................................... 52
Hardware Interface..................................................................... 52
SPI Accessible Features.............................................................. 52
Memory Map .................................................................................. 53
Reading the Memory Map Register Table............................... 53
Memory Map Register Table..................................................... 54
Applications Information .............................................................. 63
Power Supply Recommendations............................................. 63
Outline Dimensions ....................................................................... 64
Ordering Guide .......................................................................... 64
Rev. 0 | Page 2 of 64

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Data Sheet
The AD9684 has several functions that simplify the automatic
gain control (AGC) function in a communications receiver. The
programmable threshold detector allows monitoring of the
incoming signal power using the fast detect output bits of the
ADC. If the input signal level exceeds the programmable
threshold, the fast detect indicator goes high. Because this
threshold indicator has low latency, the user can quickly reduce
the system gain to avoid an overrange condition at the ADC
input. In addition to the fast detect outputs, the AD9684 also
offers signal monitoring capability. The signal monitoring block
provides additional information about the signal that the ADC
digitized.
The dual ADC output data is routed directly to the one external,
14-bit LVDS output port, supporting double data rate (DDR)
formatting. An external data clock and status bit are offered for
data capture flexibility.
The LVDS outputs have several configurations, depending on
the acceptable rate of the receiving logic device and the sampling
rate of the ADC. Multiple device synchronization is supported
through the SYNC± input pins.
AD9684
The AD9684 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V to 3.4 V capable 3-wire serial port
interface (SPI).
The AD9684 is available in a Pb-free, 196-ball ball grid array
(BGA) and is specified over the −40°C to +85°C industrial
temperature range. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Wide full power bandwidth supports intermediate
frequency (IF) sampling of signals up to 2 GHz.
2. Buffered inputs with programmable input termination ease
filter design and implementation.
3. Four integrated wideband decimation filters and NCO
blocks supporting multiband receivers.
4. Flexible SPI controls various product features and functions
to meet specific system requirements.
5. Programmable fast overrange detection and signal
monitoring.
6. SYNC± input allows synchronization of multiple devices.
7. 12 mm × 12 mm, 196-ball BGA_ED.
Rev. 0 | Page 3 of 64

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AD9684
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage Range (Programmable)
Common-Mode Voltage (VCM)
Differential Input Capacitance1
Analog Input Full Power Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
DVDD
DRVDD
SPIVDD
IAVDD1
IAVDD2
IAVDD3
IDVDD
IDRVDD
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation2
Power-Down Dissipation
Standby
Temperature Min
Full 14
Full
Full −0.3
Full
Full −6.5
Full
Full −0.6
Full −4.5
25°C
25°C
Full
25°C
Full 1.46
25°C
25°C
25°C
Full 1.22
Full 2.44
Full 3.2
Full 1.22
Full 1.22
Full 1.22
Full
Full
Full
Full
Full
Full
Full
Full
Full
Typ Max
Guaranteed
0 +0.3
0 +0.3
0 +6.5
0 +5.0
±0.5 +0.7
±2.5 +5.0
±3
−39
1.0
2.63
2.06 2.06
2.05
1.5
2
1.25 1.28
2.50 2.56
3.3 3.4
1.25 1.28
1.25 1.28
1.8 3.4
448 503
396 455
103 124
108 127
106 119
26
2.2
710
1.0
Unit
Bits
% FSR
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
V
LSB rms
V p-p
V
pF
GHz
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
W
mW
W
1 Differential capacitance is measured between the VIN+x and VIN−x pins (x = A or B).
2 Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used.
Rev. 0 | Page 4 of 64

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Data Sheet
AD9684
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless
otherwise noted.
Table 2.
Parameter1
ANALOG INPUT FULL SCALE
NOISE DENSITY2
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
SIGNAL-TO-NOISE RATIO AND DISTORTION RATIO (SINAD)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
WORST HARMONIC, SECOND OR THIRD3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
Temperature
Full
Full
Min
25°C
Full 67.5
25°C
25°C
25°C
25°C
25°C
25°C
Full 67
25°C
25°C
25°C
25°C
25°C
25°C
Full 10.8
25°C
25°C
25°C
25°C
25°C
25°C
Full 76
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Typ
2.06
−153
Max
69.2
68.6
68.4
68.0
64.4
63.8
60.5
68.7
68.5
67.6
67.2
63.8
62.5
58.3
11.1
10.9
10.8
10.8
10.3
10.1
9.5
83
85
82
86
81
76
69
−83
−85 −76
−82
−86
−81
−76
−69
Unit
V p-p
dBFS/Hz
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
Bits
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Rev. 0 | Page 5 of 64