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AMENDMENT
80C186 and 80C188 Integrated
16-Bit Microprocessors
This document amends the 80C186 and 80C188 Integrated 16-Bit Microprocessors Data Book, order #16514D, and
replaces the discontinued 80C186/80C188 CMOS High-Integration 16-Bit Microprocessors Amendment (specifica-
tions for the 20-MHz industrial operating range). This amendment consists of two parts:
n Clock generation information changes for the 80C186 and 80C188 microcontrollers. If the guidelines in this bulletin
are not followed, you may experience problems with clock start-up.
n Industrial operating information at 20 MHz. This is the same information that was published in the discontinued
80C186/80C188 CMOS High-Integration 16-Bit Microprocessors Amendment.
CLOCKING INFORMATION CHANGES
Crystal-Driven Clock Source
The internal oscillator circuit of the microcontroller is
designed to function with a parallel resonant
fundamental or third-overtone crystal. The 80C186 and
80C188 microprocessors use a crystal frequency that
is twice the processor frequency. AMD does not
recommend that you replace a crystal with an LC or RC
equivalent for any member of the Am186™ family.
The X1 and X2 signals are connected to an internal
inverting amplifier (oscillator) that provides, along with
the external feedback loading, the necessary phase
shift (Figure 1 on page 2). In such a positive feedback
circuit, the inverting amplifier has an output signal (X2)
180 degrees out of phase of the input signal (X1). The
external feedback network provides an additional 180
degree phase shift. In an ideal system, the input to X1
has 360 or zero degrees of phase shift.
The external feedback network is designed to be as
close as possible to ideal. If the feedback network is not
providing necessary phase shift, negative feedback
dampens the output of the amplifier and negatively
affects the operation of the clock generator. Values for
the loading on X1 and X2 must be chosen to provide
the necessary phase shift and crystal operation.
Selecting a Crystal
When selecting a crystal, you should always specify the
load capacitance (CL). This value can cause variance in
the oscillation frequency from the desired specified value
(resonance). The load capacitance and the loading of the
feedback network have the following relationship:
CL = (( C1 • C2)/( C1+ C2)) + CS
where CS is the stray capacitance of the circuit. Placing
the crystal and CL in series across the inverting
amplifier and tuning these values (C1, C2) allows the
crystal to oscillate at resonance. This relationship is
true for both fundamental and third-overtone operation.
Finally, there is a relationship between C1and C2. To
enhance the oscillation of the inverting amplifier, these
values must be offset with the larger load on the output
(X2). Equal values of these loads tend to balance the
poles of the inverting amplifier.
The characteristics of the inverting amplifier set limits
on the following parameters for crystals:
ESR (Equivalent Series Resistance) ........... 40 Max
Drive Level .................................................. 1 mW Max
The recommended range of values for C1and C2 are
as follows:
C1.............................................................15 pF ± 20%
C2.............................................................22 pF ± 20%
You must determine the specific values for C1 and C2.
The values are dependent on the characteristics of the
chosen crystal and board design. The C1 and C2
values include the stray capacitances of the design.
Figure 1 on page 2 shows the correct connection of the
oscillator configurations. Figure 1a shows the inverting
amplifier configuration. This is the equivalent circuitry
with the inverter integrated into the microcontroller.
Figure 1b shows the crystal configuration. The diagram
shows the correct connection for third-overtone
crystals. The fundamental mode crystals do not require
the L1 or the 200-pF capacitor. Figure 1c shows the
recommended crystal mode based on the crystal
frequency. The 80C186 and 80C188 microprocessors
use a crystal twice the CPU frequency and can use
either fundamental or third-overtone mode crystals,
depending on the CPU frequency.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product
without notice.
Publication# 16514 Rev: D Amendment/1
Issue Date: October 1998

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AMENDMENT
Crystal
C1
C2
a. Inverting Amplifier Configuration
C1
X1
Crystal
X2
C2
Microcontroller
L11
200 pF
b. Crystal Configuration
Notes:
1. Use for third overtone mode crystals. Fundamental mode
crystals do not use L1 or the 200-pF capacitor.
XTAL Frequency
20 MHz
25 MHz
32 MHz
40 MHz
50 MHz
L1 Value (Max)
12 µH ±20%
8.2 µH ±20%
4.7 µH ±20%
3.0 µH ±20%
2.2 µH ±20%
Fundamental
Third Overtone
20 MHz
25 MHz
32 MHz
40 MHz
50 MHz
c. Recommended Crystal Mode
Figure 1. Oscillator Configurations and Recommended Crystal Modes
2 80C186 and 80C188 Integrated 16-Bit Microprocessors Data Book Amendment

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AMENDMENT
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGE AT 20 MHZ
This section includes the following timings and timing waveforms at 20 MHz:
n “Read-Cycle Timings” on page 4
n “Read-Cycle Waveforms” on page 5
n “Write-Cycle Timings” on page 6
n “Write-Cycle Waveforms” on page 7
n “Interrupt Acknowledge Cycle Timings” on page 8
n “Interrupt Acknowledge Cycle Waveforms” on page 9
n “Software Halt Cycle Timings” on page 10
n “Software Halt Cycle Waveforms” on page 11
n “Clock Timings” on page 12
n “Clock Waveforms” on page 13
n “Ready, Peripheral, and Queue Status Timings” on page 14
n “Synchronous Read (SRDY) Waveforms” on page 14
n “Asynchronous Ready (ARDY) Waveforms” on page 15
n “Peripheral and Queue Status Waveforms” on page 15
n “RESET and HOLD/HLDA Timings” on page 16
n “RESET Waveforms” on page 16
n “HOLD/HLDA Waveforms (Entering HOLD)” on page 17
n “HOLD/HLDA Waveforms (Leaving HOLD)” on page 17
80C186 and 80C188 Integrated 16-Bit Microprocessors Data Book Amendment
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AMENDMENT
Read-Cycle Timings1
TA-IND=–40°C to +85°C, VCC =5 V ±10%
Preliminary
Parameter
20 MHz
# Symbol Description
Min Max Unit
General Timing Requirements (listed more than once)
1 tDVCL Data in Setup (A/D)
2 tCLDX Data in Hold (A/D)
General Timing Responses (listed more than once)
10 ns
3 ns
3 tCHSV Status Active Delay
4 tCLSH Status Inactive Delay
5 tCLAV Address Valid Delay
6 tCLAX Address Hold
7 tCLDV Data Valid Delay
8 tCHDX Status Hold Time
9 tCHLH ALE Active Delay
10 tLHLL ALE Width
11 tCHLL ALE Inactive Delay
12 tAVLL Address Valid to ALE Low2
13 tLLAX Address Hold from ALE Inactive2
14 tAVCH Address Valid to Clock High
15 tCLAZ Address Float Delay
16 tCLCSV Chip-Select Active Delay
17 tCXCSX Chip-Select Hold from Command Inactive2
18 tCHCSX Chip-Select Inactive Delay
19 tDXDL DEN Inactive to DT/R Low
20 tCVCTV Control Active Delay 13
21 tCVDEX DEN Inactive Delay
22 tCHCTV Control Active Delay 23
23 tCLLV LOCK Valid/Invalid Delay
Timing Responses (Read Cycle)
3
3
3
0
3
10
tCLCL–15 = 35
tCLCH–10 = 10
tCHCL–10 = 10
0
tCLAX = 0
3
tCLCH–10 = 10
3
0
3
3
3
3
29 ns
29 ns
25 ns
ns
25 ns
ns
20 ns
ns
20 ns
ns
ns
ns
17 ns
25 ns
ns
20 ns
ns
22 ns
22 ns
22 ns
22 ns
24 tAZRL Address Float to RD Active
25 tCLRL RD Active Delay
26 tRLRH RD Pulse Width
27 tCLRH RD Inactive Delay
28 tRHLH RD Inactive to ALE High2
29 tRHAV RD Inactive to Address Active2
0
3
2tCLCL–20 = 80
3
tCLCH–10 = 10
tCLCL–15 = 35
ns
27 ns
ns
25 ns
ns
ns
Notes:
1. All timings are measured at 1.5 V and 100-pF loading on CLKOUT unless otherwise noted. All output test conditions are with
CL = 50–100 pF (10–20 MHz). For AC tests, input VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
2. Equal loading.
3. DEN, INTA, WR.
4 80C186 and 80C188 Integrated 16-Bit Microprocessors Data Book Amendment

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Read-Cycle Waveforms
AMENDMENT
t1
t2 t3
t4
tW
CLKOUT
S2–S0
BHE/RFSH
A19/S6–A16/S3
AD15–A8
(80C188 only)
ALE
9
AD7–AD0
(80C188 only)
AD15–AD8
(80C186 only)
RD
LCS, MCS, UCS, PCS
(Note 2)
DEN
3
Status
5
BHE/RFSH
A19–A16
7
6
4 (Note 1)
BHE/RFSH S6–S3
8
10
13
12
14
11
A7–A0
A15–A8
15
24
1
2
Data
28
29
Data
25
16
26 27
17
18
20 21
DT/R
19 (Note 3)
22
23
22 (Note 5)
23 (Note 4)
LOCK
Notes:
1. Status inactive in state preceding t4.
2. If latched, A1 and A2 are selected instead of PCS5 and PCS6; only tCLCSV is applicable.
3. For write cycle followed by read cycle.
4. t1 of next bus cycle.
5. Changes in t-state preceding next bus cycle if followed by write.
80C186 and 80C188 Integrated 16-Bit Microprocessors Data Book Amendment
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