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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD720101
USB2.0 HOST CONTROLLER
The µPD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for
high-speed signaling and works up to 480 Mbps. The µPD720101 is integrated 3 host controller cores with PCI
interface and USB2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD720101 User’s Manual: S16336E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host
controller core for high-speed signaling.
• Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
• Configurable number of downstream facing ports (2 to 5)
• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2
• Supports PCI Mobile Design Guide Revision 1.1
• Supports PCI-Bus Power Management Interface Specification release 1.1
• PCI bus bus-master access
• System clock is generated by 30 MHz X’tal or 48 MHz clock input.
System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see µPD720101
User’s Manual.
• Operational registers direct-mapped to PCI memory space
• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number
µPD720101GJ-UEN
µPD720101F1-EA8
Package
144-pin plastic LQFP (Fine pitch) (20 × 20)
144-pin plastic FBGA (12 × 12)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16265EJ4V0DS00 (4th edition)
Date Published June 2004 NS CP (N)
Printed in Japan
The mark shows major revised points.
2002

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BLOCK DIAGRAM
PCI Bus
PME0
INTA0
INTB0
µPD720101
INTC0
WakeUp_Event
PCI Bus Interface
WakeUp_Event
Arbiter
WakeUp_Event
OHCI
Host
Controller
#1
OHCI
Host
Controller
#2
Root Hub
EHCI
Host
Controller
SMI0
PHY
Port 1
Port 2
Port 3
Port 4
Port 5
USB Bus
Remark INTB0/INTC0 can be shared with INTA0 through BIOS setting. (Planning)
2 Data Sheet S16265EJ4V0DS

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µPD720101
PCI Bus Interface
Arbiter
OHCI Host Controller #1
OHCI Host Controller #2
EHCI Host Controller
Root Hub
PHY
INTA0
INTB0
INTC0
SMI0
PME0
: handles 32-bit 33 MHz PCI bus master and target function which comply with PCI
specification release 2.2. The number of enabled ports is set by bit in configuration
space.
: arbitrates among two OHCI host controller cores and one EHCI host controller core.
: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5.
: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.
: handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5.
: handles USB hub function in host controller and controls connection (routing) between
host controller core and port.
: consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,
etc.
: is the PCI interrupt signal for OHCI Host Controller #1.
: is the PCI interrupt signal for OHCI Host Controller #2.
: is the PCI interrupt signal for EHCI Host Controller.
: is the interrupt signal which is specified by Open Host Controller Interface Specification
for USB Rev 1.0a and Enhanced Host Controller Interface Specification Rev 1.0. The
SMI signal of each OHCI Host Controller and EHCI Host Controller appears at this
signal.
: is the interrupt signal which is specified by PCI-Bus Power Management Interface
Specification release 1.1. Wakeup signal of each host controller core appears at this
signal.
COMPARISON WITH THE µPD720100A
EHCI revision
EHCI
OHCI
Legacy support
Clock
Package
µPD720100A
0.95
1
2
Parallel IRQ out support
48 MHz OSC or 30 MHz OSC/X’tal
176-pin BGA (FP) or 160-pin LQFP
µPD720101 (2nd generation)
1.0
1
2
No parallel IRQ support
48 MHz OSC or 30 MHz X’tal
144-pin BGA (FP) or 144-pin LQFP
Data Sheet S16265EJ4V0DS
3

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PIN CONFIGURATION
144-pin plastic LQFP (Fine pitch) (20 × 20)
µPD720101GJ-UEN
Top View
VDD
VDD
OCI1
PPON1
OCI2
PPON2
OCI3
PPON3
OCI4
PPON4
OCI5
PPON5
VCCRST0
PME0
PCLK
VBBRST0
VDD_PCI
VSS
VDD
INTA0
INTB0
INTC0
GNT0
REQ0
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
CBE30
IDSEL
VSS
VDD
1
5
10
15
20
25
30
35
µPD720101
VDD
AVSS
AVDD
105 AVSS
AVSS(R)
RREF
AVDD
VSS
100 VSS
NANDTEST
SRDTA
SRMOD
SRCLK
95 XT1/SCLK
XT2
VDD
NTEST1
TEST
90 LEGC
SMC
TEB
AMC
SMI0
85 N.C.
N.C.
CRUN0
AD0
AD1
80 VDD_PCI
AD2
AD3
AD4
AD5
75 AD6
VDD
VDD
4 Data Sheet S16265EJ4V0DS

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µPD720101
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin Name
VDD
VDD
OCI1
PPON1
OCI2
PPON2
OCI3
PPON3
OCI4
PPON4
OCI5
PPON5
VCCRST0
PME0
PCLK
VBBRST0
VDD_PCI
VSS
VDD
INTA0
INTB0
INTC0
GNT0
REQ0
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
CBE30
IDSEL
VSS
VDD
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin Name
VSS
VSS
AD23
AD22
AD21
AD20
VDD
AD19
AD18
AD17
AD16
CBE20
FRAME0
IRDY0
TRDY0
DEVSEL0
STOP0
VSS
VDD
VDD_PCI
PERR0
SERR0
PAR
CBE10
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
CBE00
AD7
VSS
VSS
Pin No.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Pin Name
VDD
VDD
AD6
AD5
AD4
AD3
AD2
VDD_PCI
AD1
AD0
CRUN0
N.C.
N.C.
SMI0
AMC
TEB
SMC
LEGC
TEST
NTEST1
VDD
XT2
XT1/SCLK
SRCLK
SRMOD
SRDTA
NANDTEST
VSS
VSS
AVDD
RREF
AVSS(R)
AVSS
AVDD
AVSS
VDD
Pin No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Pin Name
VSS
VSS
RSDM1
DM1
VDD
DP1
RSDP1
VSS
RSDM2
DM2
VDD
DP2
RSDP2
VSS
VSS
VDD
VSS
RSDM3
DM3
VDD
DP3
RSDP3
VSS
RSDM4
DM4
VDD
DP4
RSDP4
VSS
RSDM5
DM5
VDD
DP5
RSDP5
VSS
VSS
Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 9.1 k.
Pins 84 and 85 must be clamped high on the board.
Data Sheet S16265EJ4V0DS
5