AT89LP51ED2.pdf 데이터시트 (총 26 페이지) - 파일 다운로드 AT89LP51ED2 데이타시트 다운로드

No Preview Available !

Features
8-bit Microcontroller Compatible with 8051 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 16x16 Multiply–Accumulate Unit
– 256 x 8 Internal RAM
– On-chip 2KB Expanded RAM (ERAM)
• Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048 Bytes)
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 64KB of In-System Programmable (ISP) Flash Program Memory
– 4KB of EEPROM (AT89LP51ED2/ID2 Only)
– 512-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Bootloader
Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Seven 8-bit PWM Outputs
– 16-bit Programmable Counter Array
• High Speed Output, Compare/Capture
• Pulse Width Modulation, Watchdog Timer Capabilities
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Two Wire Interface 400K bit/s
– Programmable Watchdog Timer with Software Reset
– 8 General-purpose Interrupt and Keyboard Interface Pins
Special Microcontroller Features
– Dual Oscillator Support: Crystal, 32 kHz Crystal, 8 MHz Internal (AT89LP51ID2)
– Two-wire On-Chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– 8-bit Clock Prescaler
I/O and Packages
– Up to 40 Programmable I/O Lines
– Green (Pb/Halide-free) PLCC44, VQFP44, QFN44, PDIP40
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style), Input-only (Tristate)
• Push-pull CMOS Output, Open-drain
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V (Single-cycle)
8-bit Flash
Microcontroller
with 64KB
Program
Memory
AT89LP51RD2
AT89LP51ED2
AT89LP51ID2
Preliminary
Summary
3714AS–MICRO–7/11

No Preview Available !

1. Pin Configurations
1.1 44-lead VQFP
1.3 44-pad VQFN/QFN/MLF
(†MOSI/CEX2/MISO) P1.5
(†MISO/CEX3/SCK) P1.6
(†SCK/CEX4/MOSI) P1.7
(DCL) RST
(RXD) P3.0
(SDA) P4.1
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
11
SPI in remap mode
‡ AT89LP51ID2 Only
33 P0.4 (AD4)
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 POL
28 P4.0 (SCL)
27 P4.4 (ALE)
26 P4.5 (PSEN)
25 P2.7 (A15/AIN3)
24 P2.6 (A14/AIN2)
23 P2.5 (A13/AIN1)
SPI in remap mode
‡ AT89LP51ID2 Only
(†MOSI/CEX2/MISO) P1.5
(†MISO/CEX3/SCK) P1.6
(†SCK/CEX4/MOSI) P1.7
(DCL) RST
(RXD) P3.0
(SDA) P4.1
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
11
NOTE:
Bottom pad
should be
soldered to ground
33 P0.4 (AD4)
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 POL
28 P4.0 (SCL)
27 P4.4 (ALE)
26 P4.5 (PSEN)
25 P2.7 (A15/AIN3)
24 P2.6 (A14/AIN2)
23 P2.5 (A13/AIN1)
1.2 44-lead PLCC
(†MOSI/CEX2/MISO) P1.5
(†MISO/CEX3/SCK) P1.6
(†SCK/CEX4/MOSI) P1.7
(DCL) RST
(RXD) P3.0
(SDA) P4.1
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
7
8
9
10
11
12
13
14
15
16
17
SPI in remap mode
‡ AT89LP51ID2 Only
1.4 40-pin PDIP
39 P0.4 (AD4)
38 P0.5 (AD5)
37 P0.6 (AD6)
36 P0.7 (AD7)
35 POL
34 P4.0 (SCL)
33 P4.4 (ALE)
32 P4.5 (PSEN)
31 P2.7 (A15/AIN3)
30 P2.6 (A14/AIN2)
29 P2.5 (A13/AIN1)
(T2) P1.0
(SS/T2EX) P1.1
(ECI) P1.2
(CEX0) P1.3
(†SS/CEX1) P1.4
(†MOSI/CEX2/MISO) P1.5
(†MISO/CEX3/SCL) P1.6
(†SCK/CEX4/MOSI) P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
(XTAL2A) P4.7
(XTAL1A) P4.6
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VDD
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 POL
30 P4.4 (ALE)
29 P4.5 (PSEN)
28 P2.7 (A15/AIN3)
27 P2.6 (A14/AIN2)
26 P2.5 (A13/AIN1)
25 P2.4 (A12/AIN0)
24 P2.3 (A11/DAC+)
23 P2.2 (A10/DAC-)
22 P2.1 (A9)
21 P2.0 (A8)
†SPI in remap mode
2 AT89LP51RD2/ED2/ID2 Summary - Preliminary
3714AS–MICRO–7/11

No Preview Available !

AT89LP51RD2/ED2/ID2 Summary - Preliminary
1.5 Pin Description
Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description
Pin Number
VQFP
VQFN PLCC
(1)
PDIP
Symbol
Type Description
I/O P1.5: User-configurable I/O Port 1 bit 5.
I/O MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When
configured as slave, this pin is an output.
1
7
6
P1.5
I/O MOSI: SPI master-out/slave-in (Remap mode). When configured as master, this pin is an output.
When configured as slave, this pin is an input. During In-System Programming, this pin is an
input.
I/O CEX2: Capture/Compare external I/O for PCA module 2.
I/O P1.6: User-configurable I/O Port 1 bit 6.
I/O SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave,
this pin is an input.
2
8
7
P1.6
I/O MISO: SPI master-in/slave-out (Remap mode). When configured as master, this pin is an input.
When configured as slave, this pin is an output. During In-System Programming, this pin is an
output.
I/O CEX3: Capture/Compare external I/O for PCA module 3.
I/O P1.7: User-configurable I/O Port 1 bit 7.
I/O MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When
3
9
8
P1.7
configured as slave, this pin is an input.
I/O SCK: SPI Clock (Remap mode). When configured as master, this pin is an output. When
configured as slave, this pin is an input. During In-System Programming, this pin is an input.
I/O CEX4: Capture/Compare external I/O for PCA module 4.
I/O RST: External Reset input (Reset polarity depends on POL pin). The RST pin can output a pulse
4 10 9 RST
when the internal Watchdog reset or POR is active.
I DCL: Serial Debug Clock input for On-Chip Debug Interface when OCD is enabled.
5
11
10
P3.0
I/O P3.0: User-configurable I/O Port 3 bit 0.
I RXD: Serial Port Receiver Input.
6 12
P4.1
I/O P4.1: User-configurable I/O Port 4bit 1.
I/O SDA: TWI bidirectional Serial Data line.
7
13
11
P3.1
I/O P3.1: User-configurable I/O Port 3 bit 1.
O TXD: Serial Port Transmitter Output.
8
14
12
P3.2
I/O P3.2: User-configurable I/O Port 3 bit 2.
I INT0: External Interrupt 0 Input or Timer 0 Gate Input.
9
15
13
P3.3
I/O P3.3: User-configurable I/O Port 3 bit 3.
I INT1: External Interrupt 1 Input or Timer 1 Gate Input
10
16
14
P3.4
I/O P3.4: User-configurable I/O Port 3 bit 4.
I/O T1: Timer/Counter 0 External input or output.
11
17
15
P3.5
I/O P3.5: User-configurable I/O Port 3 bit 5.
I/O T1: Timer/Counter 1 External input or output.
12
18
16
P3.6
I/O P3.6: User-configurable I/O Port 3 bit 6.
O WR: External memory interface Write Strobe (active-low).
13
19
17
P3.7
I/O P3.7: User-configurable I/O Port 3 bit 7.
O RD: External memory interface Read Strobe (active-low).
I/O P4.7: User-configurable I/O Port 4 bit 7.
14 20 18
P4.7
O XTAL2A: Output from inverting oscillator amplifier A. It may be used as a port pin if the internal
RC oscillator or external clock is selected as the clock source A.
I/O P4.6: User-configurable I/O Port 4 bit 6.
15 21 19 P4.6
I XTAL1A: Input to the inverting oscillator amplifier A and internal clock generation circuits. It may
be used as a port pin if the internal RC oscillator is selected as the clock source A.
3714AS–MICRO–7/11
3

No Preview Available !

Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description
Pin Number
VQFP
VQFN PLCC
(1)
PDIP
Symbol
Type Description
16 22 20 GND
I Ground
17 23
P4.3
I/O P4.3: User-configurable I/O Port 4bit 3.
I/O DDA: Bidirectional Debug Data line for the On-Chip Debug Interface when OCD is enabled.
18
24
21
P2.0
I/O P2.0: User-configurable I/O Port 2 bit 0.
O A8: External memory interface Address bit 8.
19
25
22
P2.1
I/O P2.1: User-configurable I/O Port 2 bit 1.
O A9: External memory interface Address bit 9.
I/O P2.2: User-configurable I/O Port 2 bit 2.
20 26 23
P2.1
O DA-: DAC negative differential output.
O A10: External memory interface Address bit 10.
I/O P2.3: User-configurable I/O Port 2 bit 3.
21 27 24
P2.3
O DA+-: DAC positive differential output.
O A11: External memory interface Address bit 11.
I/O P2.4: User-configurable I/O Port 2 bit 5.
22 28 25 P2.4
I AIN0: Analog Comparator Input 0.
O A12: External memory interface Address bit 12.
I/O P2.5: User-configurable I/O Port 2 bit 5.
23 29 26 P2.5
I AIN1: Analog Comparator Input 1.
O A13: External memory interface Address bit 13.
I/O P2.6: User-configurable I/O Port 2 bit 6.
24 30 27 P2.6
I AIN2: Analog Comparator Input 2.
O A14: External memory interface Address bit 14.
I/O P2.7: User-configurable I/O Port 2 bit 7.
25 31 28 P2.7
I AIN3: Analog Comparator Input 3.
O A15: External memory interface Address bit 15.
26
32
29
P4.5
I/O P4.5: User-configurable I/O Port 4 bit 5.
O PSEN: External memory interface Program Store Enable (active-low).
27
33
30
P4.4
I/O P4.4: User-configurable I/O Port 4 bit 4.
I/O ALE: External memory interface Address Latch Enable.
28 34
P4.0
I/O
P4.0: User-configurable I/O Port 4 bit 0.
SCL: TWI Serial Clock line. This line is an output in mater mode and an input in slave mode.
29 35 31 POL
I POL: Reset polarity
30
36
32
P0.7
I/O P0.7: User-configurable I/O Port 0 bit 7.
I/O AD7: External memory interface Address/Data bit 7.
I/O P0.6: User-configurable I/O Port 0 bit 6.
31 37 33 P0.6 I/O AD6: External memory interface Address/Data bit 6.
I ADC6: ADC analog input 6.
I/O P0.5: User-configurable I/O Port 0 bit 5.
32 38 34 P0.5 I/O AD5: External memory interface Address/Data bit 5.
I ADC5: ADC analog input 5.
I/O P0.4: User-configurable I/O Port 0 bit 4.
33 39 35 P0.4 I/O AD4: External memory interface Address/Data bit 4.
I ADC4: ADC analog input 4.
I/O P0.3: User-configurable I/O Port 0 bit 3.
34 40 36 P0.3 I/O AD3: External memory interface Address/Data bit 3.
I ADC3: ADC analog input 3.
4 AT89LP51RD2/ED2/ID2 Summary - Preliminary
3714AS–MICRO–7/11

No Preview Available !

AT89LP51RD2/ED2/ID2 Summary - Preliminary
Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description
Pin Number
VQFP
VQFN PLCC
(1)
PDIP
Symbol
Type Description
I/O P0.2: User-configurable I/O Port 0 bit 2.
35 41 37 P0.2 I/O AD2: External memory interface Address/Data bit 2.
I ADC2: ADC analog input 2.
I/O P0.1: User-configurable I/O Port 0 bit 1.
36 42 38 P0.1 I/O AD1: External memory interface Address/Data bit 1.
I ADC1: ADC analog input 1.
I/O P0.0: User-configurable I/O Port 0 bit 0.
37 43 39 P0.0 I/O AD0: External memory interface Address/Data bit 0.
I ADC0: ADC analog input 0.
38 44 40 VDD
I Supply Voltage
39 1
P4.2
P4.2: User-configurable I/O Port 4bit 2.
I/O
XTAL2B: Output from low-frequency inverting oscillator amplifier B (AT89LP51ID2 only). It may
be used as a port pin if the internal RC oscillator or external clock is selected as the clock
source.
P1.0: User-configurable I/O Port 1 bit 0.
40 2
1
P1.0
I/O T2: Timer 2 External Input or Clock Output.
I/O XTAL1B: Input to the low-frequency inverting oscillator amplifier B and internal clock generation
circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source.
41 3
I/O P1.1: User-configurable I/O Port 1 bit 1.
2 P1.1
I T2EX: Timer 2 External Capture/Reload Input.
I SS: SPI Slave-Select.
42 4
3
P1.2
I/O P1.2: User-configurable I/O Port 1 bit 2.
43 5
4
P1.3
I/O P1.3: User-configurable I/O Port 1 bit 3.
I/O CEX0: Capture/Compare external I/O for PCA module 0.
44
Note:
I/O P1.4: User-configurable I/O Port 1 bit 4.
6 5 P1.4 I SS: SPI Slave-Select (Remap Mode). This pin is an input for In-System Programming
I/O CEX1: Capture/Compare external I/O for PCA module 1.
1. The AT89LP51ID2 is not available in the PDIP package.
2. Overview
The Atmel® AT89LP51RD2/ED2/ID2 is a low-power, high-performance CMOS 8-bit 8051 micro-
controller with 64KB of In-System Programmable Flash program memory. The AT89LP51ED2
and AT89LP51ID2 provide an additional 4KB of EEPROM for nonvolatile data storage. The
devices are manufactured using Atmel's high-density nonvolatile memory technology and are
compatible with the industry-standard 80C51 instruction set.
The AT89LP51RD2/ED2/ID2 is built around an enhanced CPU core that can fetch a single byte
from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock
cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the
AT89LP51RD2/ED2/ID2 CPU, standard instructions need only one to four clock cycles providing
six to twelve times more throughput than the standard 8051. Seventy percent of instructions
need only as many clock cycles as they have bytes to execute, and most of the remaining
instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS
throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current con-
sumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a
much lower speed and thereby greatly reducing power consumption and EMI. The
3714AS–MICRO–7/11
5