ISL6328.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 ISL6328 데이타시트 다운로드

No Preview Available !

NOc1No-T8nO8Rta8REc-CIEtNCOoTuOMErMRMTSMEeIcNELhNDonDEricDEwaDwFl SORwuRE.ipnPNptLeoEArrWstCiClED.ceMEonESmteNIG/rtTsNactS
Dual PWM Controller For Powering AMD SVI Split-Plane
Processors
ISL6328
The ISL6328 dual PWM controller delivers high efficiency and
tight regulation from two synchronous buck DC/DC converters.
The ISL6328 supports power control of AMD processors, which
operate from a serial VID interface (SVI). The dual output
ISL6328 features a multi-phase controller to support the Core
voltage (VDD) and a single phase controller to power the
Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-four-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in layout
and reduces the number of external components in the
multi-phase section. A single phase PWM controller with
integrated driver provides a second precision voltage regulation
system for the Northbridge portion of the processor. This
monolithic, dual controller with an integrated driver solution
provides a cost and space saving power management solution.
For applications that benefit from load line programming to reduce
bulk output capacitors, the ISL6328 features temperature
compensated output voltage droop. The multi-phase portion also
includes advanced control loop features for optimal transient
response to load application and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current balance.
Dual edge modulation is another unique feature, allowing for
quicker initial response to high di/dt load transients.
The ISL6328 supports Power Savings Mode by dropping the
number of phases when the PSI_L bit is set.
Features
• Processor Core Voltage Via Integrated Multi-Phase Power Conversion
• Configuration Flexibility
- 1 or 2-Phase Operation with Internal Drivers
- 3 or 4-Phase Operation with External PWM Drivers
• PSI_L Support
- Phase Shedding for Improved Efficiency at Light Load
- Diode Emulation in PSI mode
- Gate Voltage Optimization
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- 0.6% System Accuracy Over-Temperature
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
- Temperature Compensated
• Serial VID interface Handles up to 3.4MHz Clock Rates
• Two Level Overcurrent Protection Allows for High Current
Throttling (IDD_SPIKE)
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
June 7, 2011
FN7621.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

No Preview Available !

ISL6328
Integrated Driver Block Diagram
Channels 1 and 2 Gate Drive
GVOT
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
Northbridge Gate Drive
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
PVCC
BOOTn
UGATEn
20kΩ
10kΩ
PHASEn
LGATEn
PVCC
BOOT_NB
UGATE_NB
20kΩ
10kΩ
PHASE_NB
LGATE_NB
2 FN7621.1
June 7, 2011

No Preview Available !

ISL6328
Controller Block Diagram
VSEN_NB
ISEN_NB+
ISEN_NB-
DRPCTRL
VDDPWRGD
OFS
COMP
CSUERNRSEENT
DROOP
CONTROL
OFFSET
RGND
NB_REF
UV
LOGIC
OV
LOGIC
NB
FAULT
LOGIC
FB_NB
COMP_NB
E/A
RAMP
EN_12V
ENABLE
LOGIC
FB_PSI
FB
RGND
PWROK
SVC
SVD
VSEN
APA
OCP
CH3_OFF
PSI
+
RGND +
SVI
SLAVE
BUS
E/A
NB_REF
OV
LOGIC
APA
UV
LOGIC
OC
DUAL
OCP
I_TRIP
8
N
SOFT-START
AND
FAULT LOGIC
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
PWM1
PWM2
MOSFET
DRIVER
LDO
POWER-ON
RESET
MOSFET
DRIVER
MOSFET
DRIVER
TCOMP1
TCOMP2
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
TEMPERATURE
COMPENSATION
CSUECRNHRS1EENT
CUCRHR2ENT
SENSE
CSUECRNHRS3EENT
CSUECRNHRS4EENT
ISEN3-
ISEN4-
I_TC_IN
PWM3
PWM4
CHANNEL
CURRENT
BALANCE
I_AVG 1
N
I_TC_IN
1
8
GND
PH3/PH4
POR
CHANNEL
DETECT
EN_12V
ISEN2-
ISEN3-
ISEN4-
SLPIOGWGNMIAC3L
SLPIOGWGNMIAC4L
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PVCC
EN
VCC
GVOT
BOOT1
UGATE1
PHASE1
LGATE1
FS
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
3 FN7621.1
June 7, 2011

No Preview Available !

Typical Application
VCC
+5V
ISL6328
CS1-
CS1+
CS2-
CS2+
CS3-
CS3+
CS4-
CS4+
CS_NB-
CS_NB+
+12V
ENABLE
CORE_FB
VCC RSVD
ISEN1-
TCOMP1
ISEN1+
TCOMP2
ISEN2-
ISEN2+
PWM3
PWM4
ISEN3-
ISEN3+
ISEN4-
ISEN4+
ISL6328
PVCC
GVOT
BOOT1
ISEN_NB-
ISEN_NB+
UGATE1
PHASE1
LGATE1
DRPCTRL
FS
OFS
OCP
SVC
SVD
PWROK
VDDPWRGD
EN
APA
BOOT2
UGATE2
PHASE2
LGATE2
VSEN
RGND
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
FB_PSI
FB
COMP
VSEN_NB
FB_NB
COMP_NB
GND
PWM3
PWM4
+12V
+12V
+12V
CS1-
CS1+
+12V
+12V
CS3-
CS3+
CS2-
CS2+
CS4-
CS4+
ISL6614
BOOT1 PWM1
PWM3
PWM2
PWM4
UGATE1
PHASE1
+12V
LGATE1 PVCC
VCC
BOOT2
GND
UGATE2
PHASE2
PGND
LGATE2
CORE_FB
+12V
CS_NB-
CS_NB+
CORE
CPU
NORTHBRIDGE
4 FN7621.1
June 7, 2011

No Preview Available !

Pin Configuration
ISL6328
ISL6328
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
COMP_NB 1
36 PWM4
FB_NB 2
35 PWROK
VSEN_NB 3
34 VDDPWRGD
DRPCTRL 4
33 PHASE1
SVC 5
32 UGATE1
SVD 6
VCC 7
49
GND
31 BOOT1
30 LGATE1
RSVD 8
29 GVOT
OFS 9
28 LGATE2
OCP 10
27 BOOT2
TCOMP1 11
TCOMP2 12
26 UGATE2
25 EN
13 14 15 16 17 18 19 20 21 22 23 24
Functional Pin Descriptions
PIN NAME
COMP_NB
FB_NB
VSEN_NB
DRPCTRL
SVC
SVD
VCC
RSVD
OFS
PIN NUMBER
1
2
3
4
5
6
7
8
9
DESCRIPTION
Output of the internal error amplifier for the Northbridge regulator.
Inverting input to the internal error amplifier for the Northbridge regulator.
Non-inverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin
should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE.
Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections
via a resistor: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop On, Core
Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off.
If the resistor is tied to ground, the number of active phases in PSI mode is 1. If the resistor is tied to
VCC, the number of active phases in PSI mode is 2.
Serial VID clock input from the AMD processor.
Serial VID data bi-directional signal to and from the master device on AMD processor.
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple
using a quality 0.1µF ceramic capacitor.
RESERVED. Connect this pin directly to the VCC pin.
The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor
between FB and VSEN. The offset current is generated via an external resistor and precision internal
voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no
offset, the OFS pin should be left unconnected.
5 FN7621.1
June 7, 2011