M1008.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 M1008 데이타시트 다운로드

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UNISONIC TECHNOLOGIES CO., LTD
M1008
Preliminary
16-BIT CCD/CIS ANALOG
SIGNAL PROCESSOR
„ DESCRIPTION
The M1008 is a 16-bit CCD/CIS analog signal processor for
imaging applications. A 3-channel architecture is designed to sample
and control the outputs of tri-linear color CCD arrays. Each channel
processes one color analog signal and includes an input clamp,
Correlated Double Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), and a 16-bit A/D converter.
If there are sensors such as Contact Image Sensors (CIS) and
CMOS active pixel sensors, the CDS amplifiers are not necessary.
The 16-bit digital output is composed of high and low 8-bit
output and is assessed by two reading cycles. The internal registers
are programmed by a 3-wire serial interface which provides gain,
offset and operating mode adjustments.
The typical operation power of M1008 is 400mW in 5V power
supply.
„ FEATURES
* 400mW In 5V Operation Supply
* Under 2mA Power-Down Mode
* Built-In16-Bit 30 Msps A/D Converter
* No Missing Codes
* Input Clamp Circuitry
* Correlated Double Sampling
* Programmable Gain
* 250mV Programmable Offset
* Built-In Voltage Reference
* Programmable 3-Wire Serial Interface
* 3V/5V Digital I/O Compatibility
* Up To 25 Msps In 1-Channel Operation
* Up To 30 Msps In 2-Channel (Even-Odd) Operation
* Up To 30 Msps In 3-Channel Operation
„ ORDERING INFORMATION
Ordering Number
M1008G-P28-T
M1008G-P28-R
Package
TSSOP-28
TSSOP-28
Packing
Tube
Tape Reel
M1008G-P28-T
(1) Packing Type
(2) Package Type
(3) Halogen Free
(1) T: Tube, R: Tape Reel
(2) P28: TSSOP-28
(3) G: Halogen Free
CMOS IC
TSSOP-28
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Copyright © 2010 Unisonic Technologies Co., Ltd
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M1008
„ PIN CONFIGURATIONS
Preliminary
CMOS IC
„ PIN DESCRIPTION
PIN NO.
1
2
PIN NAME
CDSCLK1
CDSCLK2
PIN TYPE
DI
DI
PIN DESCRIPTION
CDS reference clock pulse input
CDS data clock pulse input
3 ADCCLK
DI A/D sample clock input for 3-channels mode
4
5
6
7~14
15
16
17
OE
DRVDD
DRVSS
D7~D0
SDATA
SCLK
SLOAD
DI
P
P
DO
DI/DO
DI
DI
Output enable, active low
Digital driver power
Digital driver ground
Digital data output
Serial data input/output
Clock input for serial interface
Serial interface load pulse
18,28
19,27
20
21
22
23
AVDD
AVSS
REFB
REFT
VINB
CML
P Analog supply
P Analog ground
AO Reference decoupling
AO Reference decoupling
AI Analog input, blue
AO Internal reference output
24 VING
AI Analog input, green
25 OFFSET
AO Clamp bias level decoupling
26 VINR
AI Analog input, red
Note: I=input, O=output, I/O=input/output, P=power supply, G=ground
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www.unisonic.com.tw
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M1008
„ BLOCK DIAGRAM
Preliminary
CMOS IC
UNISONIC TECHNOLOGIES CO., LTD
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M1008
Preliminary
CMOS IC
„ ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
Input Voltage
Ambient Operation Temperature
Storage Temperature
VDD
VIN
TOPR
TSTG
VSS-0.3 to VSS+5.5
VSS-0.3 to VDD+0.3
-25 ~ +75
-50 ~ +125
V
V
°C
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
„ ELECTRICAL CHARACTERISTICS (AVDD=5V, DVDD=3V, TA=25°C. Unless otherwise specified)
PARAMETER
Analog Power Supply
Digital Power Supply
3-Channel Mode with CDS
2-Channel Mode with CDS
1-Channel Mode with CDS
ADC Resolution
Integral Nonlinear (INL)
Differential Nonlinear (DNL)
Offset Error
Gain Error
Full-Scale Input Range
Input Limits
Input Current
PGA Gain at Minimum
PGA Gain at Maximum
PGA Gain Resolution
Programmable Offset at Minimum
Programmable Offset at Maximum
Offset Resolution
Operating
Total Power Consumption
High Level Input Voltage
(CDSCLK1, CDSCLK2, ADCCLK,
OE , SCK, SLOAD)
Low Level Input Voltage
(CDSCLK1, CDSCLK2, ADCCLK,
OE , SCK, SLOAD)
High Level Input Voltage (SDATA)
Low Level Input Voltage (SDATA)
High Level Input Current
Low Level Input Current
Input Capacitance
High Level Output Voltage
(SDATA, D0~D7)
Low Level Output Voltage
(SDATA, D0~D7)
High Level Output Current
Low Level Output Current
SYMBOL
VADD
VDRDD
tMAX3
tMAX2
tMAX1
RFS
VI(LIMIT)
IIN
TA
Ptot
VIH
VIL
VIH1
VIL1
IIH
IIL
CIN
VOH
VOL
IOH
IOL
TEST CONDITION
MIN
4.75
3
30
30
25
-1
-100
AVSS-0.3
0
TYP
5
5
16
±32
5
2.0
5
10
1
5.85
6
-250
250
9
400
MAX UNIT
5.25 V
5.25 V
MSPS
MSPS
MSPS
Bits
LSB
1 LSB
100 mV
%FSR
AVDD+0.3
VP-P
V
nA
V/V
V/V
Bits
mV
mV
Bits
70 °C
mW
0.8*VDD
V
0.8*VDD
VDD-0.5
10
10
10
1
1
0.2*VDD V
0.2*VDD
V
V
uA
uA
pF
V
0.5 V
mA
mA
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M1008
„ TIMING SPECIFICATION
PARAMETER
3-Channel Pixel Rate
2-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulse Width
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Rising to CDSCLK1 Falling
ADCCLK Rising to CDSCLK2 Falling
Analog Sampling Delay
3-CHANNEL Mode Only
CDSCLK2 Falling to CDSCLK1 Rising
CDSCLK2 Falling to ADCCLK Rising
2-CHANNEL Mode Only
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Rising
CDSCLK2 Falling to CDSCLK1 Rising
1-CHANNEL Mode Only
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDARA Hold Time
Falling to SDATA Valid
DATA OUTPUT
Output Delay
Latency(Pipeline Delay)
Preliminary
SYMBOL
tPRA
tPRB
tPRC
tADCLK
tC1
tC2
tC1C2
tADC1
tADC2
tAD
taC2C1
taC2ADR
tbC2ADR
tbC1ADR
tbC2C1
tcC2ADR
tcC1ADF
tcC2C1
fSCLK
tLS
tLH
tDS
tDH
tRDV
tOD
TEST CONDITION
CMOS IC
MIN TYP MAX UNIT
100 ns
66 ns
40 ns
16 ns
12 ns
12 ns
0 ns
0 ns
0 ns
5 ns
30
30
30
15
15
20
0
15
10
10
10
10
10
10
8
9
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
Cycles
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