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DATASHEET
VR11.1, 6-Phase PWM Controller with Phase Dropping,
Droop Disabled and Load Current Monitoring Features
ISL6336D
The ISL6336D controls voltage regulators by driving up to 6
interleaved synchronous-rectified buck channels in parallel.
This multiphase architecture results in multiplying channel
ripple frequency and reducing input and output ripple currents.
Lower ripple results in fewer components, lower cost, reduced
power dissipation, and smaller implementation area.
The ISL6336D utilizes Intersil’s proprietary Active Pulse
Positioning (APP), Adaptive Phase Alignment (APA)
modulation scheme, active phase adding and dropping to
achieve and maintain the extremely fast transient response
with fewer output capacitors and high efficiency from light to
full load.
The ISL6336D is designed to be completely compliant with
Intel VR11.1 specifications with exception of droop disabled. It
accurately reports the load current via the IMON pin to the
microprocessor, which sends an active low PSI# signal to the
controller at low power mode. The controller then enters 1- or
2-phase operation option to reduce magnetic core and
switching losses, yielding high efficiency at light load. After the
PSI# signal is deasserted, the dropped phase(s) are added
back to sustain heavy load transient response and efficiency.
The ISL6336D senses the output current continuously by
utilizing patented techniques to measure the voltage across
the dedicated current sense resistor or the DCR of the output
inductor. Current sensing circuits also provide the needed
signals for channel-current balancing, average overcurrent
protection and individual phase current limiting. An NTC
thermistor’s temperature is sensed via the TM pin and
internally digitized for thermal monitoring and for integrated
thermal compensation of the current sense elements.
A unity gain, differential amplifier is provided for remote
voltage sensing and completely eliminates any potential
difference between remote and local grounds. This improves
regulation and protection accuracy. The threshold-sensitive
enable input is available to accurately coordinate the start-up
of the ISL6336D with any other voltage rail. Dynamic VID™
technology allows seamless on-the-fly VID changes. The offset
pin allows accurate voltage offset settings that are
independent of VID setting.
Features
• Intel VR11.1 compliant with droop disabled
• Proprietary active pulse positioning (APP) and adaptive
phase alignment (APA) modulation scheme
• Proprietary active phase adding and dropping for high light
load efficiency
• Precision multiphase core voltage regulation
- Differential remote voltage sensing
- 0.5% closed-loop system accuracy over load, line and
temperature
- Bidirectional, adjustable reference-voltage offset
• Precision resistor or DCR differential current sensing
- Accurate channel-current balancing
- Accurate load current monitoring via IMON pin
• Microprocessor voltage identification input
- Dynamic VID™ technology for VR11.1 requirement
- 8-bit VID, VR11 compatible
• Average overcurrent protection and channel current limit
• Precision overcurrent protection on IMON pin
• Thermal monitoring and overvoltage protection
• Integrated programmable temperature compensation
• Integrated open sense line protection
• 1- to 6-phase operation, coupled inductor compatibility
• Adjustable switching frequency up to 1MHz per phase
• Package option
- QFN compliant to JEDEC PUB95 MO-220 QFN - quad flat
no leads - product outline
• Pb-free (RoHS compliant)
October 6, 2014
FN8320.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) and Dynamic VID are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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ISL6336D
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PWM Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PWM and PSI# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Channel-Current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output-Voltage Offset Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Dynamic VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Current Sense Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VR_RDY Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal Monitoring (VR_HOT/VR_FAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Temperature Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Integrated Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current Sensing Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Voltage-Regulator (VR) Design Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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ISL6336D
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6336DIRZ
ISL6336D IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6336D. For more information on MSL please see TB363.
INTERSIL PN
ISL6336
ISL6336A
ISL6336B
ISL6336D
ISL6334
ISL6334A
ISL6334B
ISL6334C
ISL6334D
NUMBER OF PHASES
6
6
6
6
4
4
4
4
4
TABLE 1. ISL6336x/4x FAMILY SUMMARY
DIODE
EMULATION
DROOP
H_CPURST_N INPUT
Yes Yes
No
No Yes
No
Yes Yes
Yes
No No
No
Yes Yes
No
No Yes
No
Yes Yes
Yes
No No
Yes
No No
No
TARGETED APPLICATIONS
VR11.x CPU
VR11.x CPU
VR11.x CPU
General Purpose, Memory
VR11.x CPU
VR11.x CPU
VR11.x CPU
VR11.x CPU
General Purpose, Memory
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Pin Configuration
ISL6336D
ISL6336D
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
VID7 1
36 PWM3
VID6 2
35 ISEN3-
VID5 3
VID4 4
VID3 5
VID2 6
VID1 7
VID0 8
PSI# 9
OFS 10
IMON 11
DAC 12
GND
34 ISEN3+
33 ISEN1+
32 ISEN1-
31 PWM1
30 PWM4
29 ISEN4-
28 ISEN4+
27 ISEN2+
26 ISEN2-
25 PWM2
13 14 15 16 17 18 19 20 21 22 23 24
Pin Descriptions
PIN #
1, 2, 3, 4,
5, 6, 7, 8
9
10
11
12, 13
14
PIN NAME
DESCRIPTION
VID7, VID6, VID5, VID4, These are the inputs to the internal DAC that generate the reference voltage for output regulation. All VID pins
VID3, VID2, VID1, VID0 have no internal pull-up current sources until after TD3. Connect these pins either to open-drain outputs with
external pull-up resistors or to active pull-up outputs, as high as VCC plus 0.3V.
PSI#
A low input signal indicates the low power mode operation of the processor. The controller drops the number of
active phases to single or 2-phase operation, according to the logic on Table 2 on page 14. The PSI# pin, SS, and
FS pins are used to program the controller in operation of noncoupled, 2-Phase coupled, or (n-x)-Phase coupled
inductors when PSI# is asserted (active low). Different cases yield different PWM output behavior on both
dropped phase(s) and remaining phase(s) as PSI# is asserted and deasserted. A high input signal pulls the
controller back to normal operation.
OFS The OFS pin can be used to program a DC offset current, which will generate a DC offset voltage between the
REF and DAC pins. The offset current is generated via an external resistor and precision internal voltage
references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS
pin should be left unterminated.
IMON
IMON is the output pin of sensed, thermally compensated (if internal thermal compensation is used) average
current. The voltage at IMON pin is proportional to the load current and the resistor value, and internally clamped
to 1.11V plus the remote ground potential difference. If the clamped voltage (1.11V) is triggered, it will initiate the
overcurrent shutdown. By choosing the proper value for the resistor at IMON pin, the overcurrent trip level can be
set to be lower than the fixed internal overcurrent threshold. During the dynamic VID, the OCP function of this pin
is disabled to avoid false triggering. Tie it to GND if not used.
DAC, REF
The DAC pin is the output of the precision internal DAC reference. The REF pin is the positive input of the Error
Amplifier. In typical applications, a 1kΩ, 1% resistor is used between DAC and REF to generate a precision offset
voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground
or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VID™
operations.
APA The APA pin is used to adjust the Adaptive Phase Alignment trip level. A 50µA current source flows into this pin. A
resistor connected from this pin to COMP sets the voltage trip level. A small decoupling capacitor should be placed
in parallel with the resistor for high frequency decoupling.
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ISL6336D
Pin Descriptions (Continued)
PIN #
PIN NAME
DESCRIPTION
16, 15
FB, COMP
Inverting input and output of the error amplifier respectively. FB can be connected to VDIFF through a resistor.
COMP is tied back to FB through an external R-C network to compensate the regulator.
17, 19, 18
VDIFF, VSEN, RGND
VSEN and RGND form the precision differential remote-sense amplifier. This amplifier converts the differential
voltage of the remote output to a single-ended voltage referenced to local ground. VDIFF is the amplifier’s output
and the input to the regulation and protection circuitry. Connect VSEN and RGND to the sense pins of the remote
load.
20
TCOMP
Temperature compensation scaling input. The voltage sensed on the TM pin is utilized as the temperature input to
adjust IMON and the overcurrent protection limit to effectively compensate for the temperature coefficient of the
current sense element. To implement the integrated temperature compensation, a resistor divider circuit is needed
with one resistor being connected from TCOMP to VCC of the controller and another resistor being connected from
TCOMP to GND. Changing the ratio of the resistor values will set the gain of the integrated thermal compensation.
When integrated temperature compensation function is not used, connect TCOMP to GND.
21 VCC Supplies the power necessary to operate the chip. The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR
threshold. Connect this pin directly to a +5V supply.
22, 23,
26, 27,
28, 29,
32, 33,
34, 35,
38, 39
ISEN5+, ISEN5-,
ISEN2-, ISEN2+,
ISEN4+, ISEN4-,
ISEN1-, ISEN1+,
ISEN3+, ISEN3-,
ISEN6-, ISEN6+
The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is
used for channel current balancing and overcurrent protection. Inactive channels should have their respective
current sense inputs left open (for example, open ISEN6+ and ISEN6- for 5-phase operation).
For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN. The voltage across the sense capacitor is proportional
to the inductor current. Therefore, the sense current is proportional to the inductor current and scaled by the DCR
of the inductor and RISEN. To match the time delay of the internal circuit, a capacitor is needed between each
ISEN+ pin and GND, as described in “Current Sensing” on page 14.
24, 25, 30,
31, 36, 37
PWM5, PWM2, PWM4,
PWM1, PWM3, PWM6
Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number
of active channels is determined by the state of PWM2, PWM3, PWM4, PWM5 and PWM6. Tie PWM2 to VCC to
configure for 1-phase operation. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to
configure for 3-phase operation. Tie PWM5 to VCC to configure for 4-phase operation. Tie PWM6 to VCC to
configure for 5-phase operation. In addition, tie PSI# to GND to configure for single phase operation as well.
40
EN_PWR
This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN_PWR through
an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.875V, the ISL6336D is active depending on status of the EN_VTT,
the internal POR, and pending fault states. Driving EN_PWR below 0.745V will clear all fault states and prime
the ISL6336D to soft-start when reenabled.
41
EN_VTT
This pin is another threshold-sensitive enable input for the controller. It’s typically connected to VTT output of VTT
voltage regulator in the computer mother board. When EN_VTT is driven above 0.875V, the ISL6336D is active
depending on status of the EN_PWR, the internal POR, and pending fault states. Driving EN_VTT below 0.745V
will clear all fault states and prime the ISL6336D to soft-start when reenabled.
42 FS Use this pin to set up the desired switching frequency. A resistor placed from FS to ground/VCC will set the
switching frequency. The relationship between the value of the resistor and the switching frequency will be
approximated by Equation 3. This pin is also used with SS and PSI# pins for phase dropping decoding (see
Table 2 on page 14).
43 SS Use this pin to set up the desired start-up oscillator frequency. A resistor placed from SS to ground/VCC will set
up the soft-start ramp rate. The relationship between the value of the resistor and the soft-start ramp-up time
will be approximated by Equations 14 and 15. This pin is also used with FS and PSI# pins for phase dropping
decoding (see Table 2 on page 14).
44 OVP The overvoltage protection output indication pin. This pin can be pulled to VCC and is latched when an
overvoltage condition is detected. When the OVP indication is not used, keep this pin open.
45
VR_RDY
VR_RDY indicates that soft-start has completed and the output voltage is within the regulated range around the
VID setting. It is an open-drain logic output. When OCP or OVP occurs, VR_RDY will be pulled to low. It will also
be pulled low if the output voltage is below the undervoltage threshold.
46
VR_FAN
VR_FAN is an output pin with open-drain logic output. It will be pulled low if the measured VR temperature is less
than a certain level, and open when the measured VR temperature reaches a certain level. An external pull-up
resistor is needed.
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FN8320.0
October 6, 2014