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®
Data Sheet
X9110
Dual Supply/Low Power/1024-Tap/SPI Bus
February 13, 2008
FN8158.3
Single Digitally-Controlled (XDCP™)
Potentiometer
The X9110 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Functional Diagram
VCC
Features
• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for write, read, and transfer operations
of the potentiometer
• Wiper Resistance, 40Ω Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on Power-up
• Standby Current < 3µA Max
• System VCC: 2.7V to 5.5V Operation
• Analog V+/V-: -5V to +5V
• 100kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Dual Supply Version of the X9111
• Low Power CMOS
• Pb-Free Available (RoHS Compliant)
Pinout
V+
S0
A0
SCK
WP
SI
VSS
X9110
14 LD TSSOP
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
VCC
RL
RH
RW
HOLD
CS
V-
RH V+
SPI
BUS
INTERFACE
ADDRESS
DATA
STATUS
BUS
INTERFACE &
CONTROL
WRITE
READ
TRANSFER
CONTROL
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
WIPER
100kΩ
1024-TAPS
POT
VSS NC NC
RW RL
V-
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas INC. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X9110
Ordering Information
PART NUMBER
VCC LIMITS POTENTIOMETE
PART MARKING
(V)
R RANGE (kΩ)
TEMP
RANGE (°C)
PACKAGE
PKG.
DWG. #
X9110TV14
X9110TV
5 ±10
100
0 to +70
14 Ld TSSOP
M14.173
X9110TV14Z* (Note)
X9110TV Z
0 to +70
14 Ld TSSOP (Pb-free) M14.173
X9110TV14I
X9110TV I
-40 to +85 14 Ld TSSOP
M14.173
X9110TV14IZ (Note)
X9110TV Z I
-40 to +85 14 Ld TSSOP (Pb-free) M14.173
X9110TV14-2.7
X9110TV F
2.7 to 5.5
0 to +70
14 Ld TSSOP
M14.173
X9110TV14Z-2.7 (Note) X9110TV Z F
0 to +70
14 Ld TSSOP (Pb-free) M14.173
X9110TV14I-2.7
X9110TV G
-40 to +85 14 Ld TSSOP
M14.173
X9110TV14IZ-2.7* (Note) X9110TV Z G
-40 to +85 14 Ld TSSOP (Pb-free) M14.173
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Detailed Functional Diagram
VCC
V+
HOLD
CS
SCK
SO
SI
A0
WP
INTERFACE
AND
CONTROL
CIRCUITRY
DATA
CONTROL
POWER ON
RECALL
DR0
DR2
DR1
DR3
WIPER
COUNTER
REGISTER
(WCR)
100kΩ
1024-TAPS
RH
RL
RW
VSS
V-
2 FN8158.3
February 13, 2008

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X9110
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in
filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent systems
Pin Descriptions
PIN
(TSSOP)
1
2
3
4
5
6
7
8
SYMBOL
V+
SO
A0
SCK
WP
SI
VSS
V-
FUNCTION
Analog Supply Voltage
Serial Data Output
Device Address
Serial Clock
Hardware Write Protect
Serial Data Input
System Ground
Analog Supply Voltage
9 CS Chip Select
10 HOLD Device Select. Pause the Serial Bus
Pin Descriptions (Continued)
PIN
(TSSOP)
SYMBOL
FUNCTION
11 RW Wiper Terminal of the Potentiometer
12 RH High Terminal of the Potentiometer
13 RL Low Terminal of the Potentiometer
14
VCC
System Supply Voltage
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out on the falling edge
of the serial clock.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the pots and pot registers are input
on this pin. Data is latched by the rising edge of the serial
clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9110.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while SCK is
LOW. To resume communication, HOLD is brought HIGH, again
while SCK is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
DEVICE ADDRESS (A0)
The address input is used to set the 8-bit slave address. A
match in the slave address serial data stream A0 must be
made with the address input (A0) in order to initiate
communication with the X9110.
CHIP SELECT (CS)
When CS is HIGH, the X9110 is deselected and the SO pin
is at high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS LOW
enables the X9110, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the
Data Registers.
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X9110
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
10
REGISTER 2
(DR2)
If WCR = 000[HEX] then RW = RL
If WCR = 3FF[HEX] then RW = RH
REGISTER 1
(DR1)
10
REGISTER 3
(DR3)
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
RH
RL
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
RW
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin is
the system ground.
ANALOG SUPPLY VOLTAGES (V+ AND V-)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper switches
while the V- supply is used to bias the switches and the
internal P+ substrate of the integrated circuit. Both of these
supplies set the voltage limits of the potentiometer.
Principles Of Operation
Device Description
SERIAL INTERFACE
The X9110 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked-in
on the rising SCK. CS must be LOW and the HOLD and WP
pins must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
ARRAY DESCRIPTION
The X9110 is comprised of a resistor array (Figure 1). The
array contains the equivalent of 1023 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (RW)
output. Within the individual array only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to
select, and enable, one of 1024 switches.
WIPER COUNTER REGISTER (WCR)
The X9110 contains a Wiper Counter Register (see Table 1)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways: (1) it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); (2) it
4 FN8158.3
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X9110
may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its data register zero
(DR0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9110 is powered-down. Although
the register is automatically loaded with the value in DR0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
DATA REGISTERS (DR)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.
DR[9:0] is used to store one of the 1024 wiper position
(0~1023) (see Table 2).
STATUS REGISTER (SR)
This 1-bit status register is used to store the system status
(see Table 3).
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
progress.
• When WIP=0, indicates that no high-voltage write cycle is
in progress.
TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used To Store The Current Wiper Position (Volatile, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
VVVVVVVVVV
(MSB)
(LSB)
BIT 9
NV
MSB
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Non-Volatile, NV)
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
NV NV NV NV NV NV NV NV
TABLE 3. STATUS REGISTER, SR (1-BIT)
WIP
(LSB)
BIT 0
NV
LSB
5 FN8158.3
February 13, 2008