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Advanced Double-Ended PWM Controller
ISL6742B
The ISL6742B is a high-performance double-ended PWM
controller with advanced synchronous rectifier control and
current limit features. It is suitable for both current- and
voltage-mode control methods.
The ISL6742B includes complemented PWM outputs for
synchronous rectifier (SR) control. The complemented outputs
may be dynamically advanced or delayed relative to the main
outputs using an external control voltage.
Its advanced current sensing circuitry employs sample and
hold methods to provide a precise average current signal.
Suitable for average current limiting, a technique which
virtually eliminates the current tail-out common to peak
current limiting methods, it is also applicable to current
sharing circuits and average current mode control.
This advanced BiCMOS design features an adjustable oscillator
frequency up to 2MHz, internal over-temperature protection,
precision deadtime control, and short propagation delays.
Additionally, Multi-Pulse Suppression ensures alternating output
pulses at low duty cycles where pulse skipping may occur.
Ordering Information
PART #
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL6742BAAZA ISL6742 BAAZ -40 to +105 16 Ld QSOP M16.15A
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL6742B. For more information on MSL, please see tech
brief TB363.
Features
• Synchronous rectifier control outputs with adjustable
delay/advance
• Adjustable average current signal
• 3% tolerance cycle-by-cycle peak current limit
• Fast current sense to output delay
• Adjustable oscillator frequency up to 2MHz
• Adjustable deadtime control
• Voltage- or current-mode operation
• Separate RAMP and CS inputs for voltage feed-forward or
current-mode applications
• Tight tolerance error amplifier reference over line, load, and
temperature
• 175µA start-up current
• Supply UVLO
• Adjustable soft-start
• 70ns leading edge blanking
• Multi-pulse suppression
• Internal over-temperature protection
• Pb-Free (RoHS compliant)
Applications
• Half-bridge, full-bridge, interleaved forward, and push-pull
converters
• Telecom and datacom power
• Wireless base station power
• File server power
• Industrial power systems
Related Literature
• See AN1890, “ISL6742BEVAL3Z Power Converter 36V to
75V Input, 12V Output Up to 10A”
January 31, 2014
FN8565.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
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ISL6742B
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application - Telecom Primary Side Control Half-Bridge Converter with Synchronous Rectification . . . . . . . . . . . . . . 6
Typical Application - High Voltage Input Secondary Side Control Full-Bridge Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Soft-Start Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overcurrent Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Voltage Feed-Forward Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Implementing Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Synchronous Rectifier Outputs and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Slope Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parallel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Average Current Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fault Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ground Plane Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Pin Configuration
ISL6742B
ISL6742B
(16 LD QSOP)
TOP VIEW
VREF 1
VERR 2
RTD 3
CT 4
FB 5
RAMP 6
CS 7
IOUT 8
16 SS
15 VADJ
14 VDD
13 OUTA
12 OUTB
11 OUTAN
10 OUTBN
9 GND
Pin Descriptions
PIN # SYMBOL
DESCRIPTION
1 VREF The 5V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass to GND with a 0.1µF to
2.2µF low ESR capacitor.
2 VERR The VERR pin is the output of the error amplifier and controls the inverting input of the PWM comparator. Feedback compensation
components connect between VERR and FB. There is a nominal 1mA pull-up current source connected to VERR. Soft-start is
implemented as a voltage clamp on the VERR signal.
The outputs, OUTA and OUTB, reduce to 0% duty cycle when VERR is pulled below 0.6V. OUTAN and OUTBN, the complements of
OUTA and OUTB, respectively, go to 100% duty cycle when this occurs.
3 RTD This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor connected between this pin and
GND determines the magnitude of the current that discharges CT. The CT discharge current is nominally 20x the resistor current.
The PWM deadtime is determined by the timing capacitor discharge duration. The voltage at RTD is nominally 2V. The minimum
recommended value of RTD is 2.00k.
4 CT The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal 200µA current source and
discharged with a user adjustable current source controlled by RTD.
5 FB FB is the inverting input to the error amplifier (EA). The amplifier may be used as the error amplifier for voltage feedback or used
as the average current limit amplifier (IEA). If the amplifier is not used, FB should be grounded.
6 RAMP This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at the termination of the
PWM signal. A sawtooth voltage waveform is required at this input. For current-mode control this pin is connected directly to CS and
the current loop feedback signal is applied to both inputs. For voltage-mode control, the oscillator sawtooth waveform may be
buffered and used to generate an appropriate signal, or RAMP may be connected to the input voltage through an RC network for
voltage feed forward control, or RAMP may be connected to VREF through an RC network to produce the desired sawtooth
waveform.
7 CS This is the input to the overcurrent comparator and the average current sample and hold circuit. The overcurrent comparator
threshold is set at 1V nominal. The CS pin is shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal
clock and the external power switch. This delay may result in CS being discharged prior to the power switching device being turned
off.
8 IOUT Output of the 4x buffer amplifier of the sample and hold circuitry that captures and averages the CS signal.
9 GND Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance
layout is necessary. Ground planes and short traces are highly recommended.
11, 10 OUTAN and These outputs are the complements of OUTA and OUTB, respectively. These outputs are suitable for control of synchronous
OUTBN rectifiers. The phase relationship between each output and its complement is set by a control voltage applied to VADJ.
13, 12 OUTA and These paired outputs are the pulse width modulated outputs for controlling the switching FETs in alternate sequence.
OUTB
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ISL6742B
Pin Descriptions (Continued)
PIN #
14
15
16
SYMBOL
DESCRIPTION
VDD VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a 0.1µF or larger high frequency
ceramic capacitor as close to the VDD and GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out (UVLO). The start and stop thresholds track each other resulting in
relatively constant hysteresis.
VADJ
A 0V to 5V control voltage applied to this input sets the relative delay or advance between OUTA/OUTB and OUTAN/OUTBN.
Voltages below 2.425V result in OUTAN/OUTBN being advanced relative to OUTA/OUTB. Voltages above 2.575V result in
OUTAN/OUTBN being delayed relative to OUTA/OUTB. A voltage of 2.50V ±75mV results in zero phase difference. A weak internal
50% divider from VREF results in no phase delay if this input is left floating.
The range of phase delay/advance is either zero or 40ns to 300ns with the phase differential increasing as the voltage deviation
from 2.5V increases. The relationship between the control voltage and phase differential is non-linear. The gain (Δt/ΔV) is low for
control voltages near 2.5V and rapidly increases as the voltage approaches the extremes of the control range. This behavior
provides the designer increased accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR outputs (VADJ < 2.425V), the delay time should not exceed 90% of the
deadtime as determined by RTD and CT.
SS Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor
determines the rate of increase of the duty cycle during start-up. Although no minimum value of capacitance is required, it is
recommended that a value of at least 100pF be used for noise immunity.
SS may also be used to inhibit the outputs by grounding through a small transistor in an open collector/drain configuration.
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Functional Block Diagram
VDD
GND
VREF
IOUT
UVLO
OVER-
TEMPERATURE
PROTECTION
4X
VREF
SAMPLE
AND
HOLD
CT
RTD
SS
OSCILLATOR
VREF
PWM
STEERING
LOGIC
VDD
DELAY/
ADVANCE
TIMING
CONTROL
+
- 1.00V
OVERCURRENT
COMPARATOR
+70ns
LEADING
EDGE
BLANKING
OUTA
OUTB
OUTAN
OUTBN
VADJ
CS
PWM
COMPARATOR
+
-
80mV
0.33
SOFT-START
CONTROL
VREF
1mA
RAMP
+ 0.6V
-
VERR
FB