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Data Sheet
September 8, 2015
ISL6422B
FN6486.2
Dual Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6422B is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is consists of two independent current-
mode boost PWMs and two low-noise linear regulators along
with the circuitry required for 22kHz tone generation,
modulation and I2C device interface. The device makes the
total LNB supply design simple, efficient and compact with
low external component count.
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 0.8V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM
can be controlled in two ways, full control from I2C using the
VTOP1, VTOP2 and VBOT1, VBOT2 bits or set the I2C to
the lower range ie 13V/14V and switch to higher range ie
18V/19V with the SELVTOP1, SELVTOP2 pins. All the
functions on this IC are controlled via the I2C bus by writing
8 bits words onto the System Registers (SR). The same
register can be read back, and four bits per output will report
the diagnostic status. Separate enable commands sent on the
I2C bus provide independent standby mode control for each
PWM and linear combination, disabling the output into
shutdown mode. Each output channel is capable of providing
750mA of continuous current. The overcurrent limit can be
digitally programmed.
The External modulation input EXTM1, EXTM2 can accept a
modulated DiSEqC command and transfer it symetrically to
the output. Alternatively the EXTM1, EXTM2 pins can be
used to modulate the continuous internal tone.
The FLT pin serves as an interrupt for the processor when any
condition turns OFF the LNB controller (Over- Temperature,
Overcurrent, Disable). The nature of the fault can be read of
the I2C registers.
Features
• Single Chip Power Solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC/DC Converter and I2C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with >92% Efficiency
- Selectable 13.3V or 18.3V Outputs
- Digital Cable Length Compensation (1V)
- I2C and Pin Controllable Output
• Output Back Bias Capability of 28V
• I2C Compatible Interface for Remote Device Control
• Four level Slave Address 0001 00XX
• 2.5V/3.3V/5V Logic Compatible
• External Pins to Toggle Between V and H Polarization
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
- External Modulation Input
• Internal Over-Temperature Protection and Diagnostics
• Internal OV, UV, Overload and Overtemp Flags (Visible on
I2C)
• FLT Signal
• LNB Short-Circuit Protection and Diagnostics
• QFN and EPTSSOP Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
Ordering Information
PART NUMBER PART
(Note)
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6422BERZ* 6422B ERZ -20 to +85 40 Ld 6x6 QFN L40.6x6
ISL6422BEVEZ*
(No longer
available,
Recommended
Replacement
ISL6422BERZ)
6422B EVEZ -20 to +85 38 Ld EPTSSOP M38.173B
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas LLC 2007, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinouts
ISL6422B
ISL6422B
(38 LD EPTSSOP)
TOP VIEW
CS2 1
38 TXT2
VSW2 2
37 SELVTOP2
VSW2 3
36 TCAP2
GATE2 4
35 AGND
PGND2 5
EDEXTM2 6
ORTSGND 7
PPFLT 8
SUSDA 9
E ORSCL 10
BLADDR0 11
AILAADDR1 12
AVEXTM1 13
ERBYP 14
ONGPGND1 15
NO L GATE1 16
34 VOUT2
33 TDIN2
32 TDOUT2
31 CPVOUT
30 CPSWOUT
29 CPSWIN
28 VCC
27 TDOUT1
26 TDIN1
25 VOUT1
24 AGND
23 TCAP1
VSW1 17
22 SELVTOP1
VSW1 18
21 NC
CS1 19
20 TXT1
ISL6422B
(40 LD 6X6 QFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
EXTM2 1
SGND 2
NC 3
FLT 4
SDA 5
SCL 6
ADDR0 7
ADDR1
EXTM1
8
9
BYP 10
30 VOUT2
29 TDIN2
28 TDOUT2
27 CPVOUT
26 CPSWOUT
25 CPSWIN
24 VCC
23 TDOUT1
22 TDIN1
21 VOUT1
11 12 13 14 15 16 17 18 19 20
2 FN6486.2
September 8, 2015

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Block Diagram
17
COUNTER
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
OLF1
DCL1
12 GATE1
PWM
LOGIC
Q
S
CLK1
OC1
PGND1
11
15 CS1
CS ILIM1
AMP
SLOPE
COMPENSATION
TDOUT1
23
TONE
DECODER
22 TDIN1
TXT1
VREF1
14 VSW1
20,21
19,32
VO1
AGND
24 VCC
ON CHIP
LINEAR
UVLO
2
SGND
POR
SOFT-START
INT 5V
SOFT-START
EN1/EN2
NOTE:
10
1. Pinouts shown are for the QFN package.
16
56
8
4
7
OLF2
DCL2
OVERCURRENT
PROTECTION
LOGIC SCHEME 2
COUNTER
BAND GAP
REF VOLTAGE
REF
VOLTAGE
ADJ1
OC2
SDA SCL ADDR1
ADDR0OUVFO11UVF2
ISEL1L AND
ISEL1H
EN1
ENT1
OLF1 FLT OLF2
I2C
INTERFACE
ISEL2L AND
ISEL2H
EN2
ENT2
OTF
VTOP1 VBOT1
DCL
VBOT2 VTOP2
CLK2
PWM
LOGIC
Q
S
GATE2
PGND2
ILIM2 CS
AMP
SLOPE
COMPENSATION
CS2
BGV
CLK1
OSC.
1.1MHz
CLK2
DIV AND
WAVE SHAPING
TONE
INJ
CKT 1
INT
TONE
TONE
INJ
CKT 2
BGV
REF
VOLTAGE
ADJ2
VREF2
SELVTOP2
VSW2
39
40
36
34
37
+-
+-
VO2
30,31
EXT TONE CKT
ENT1
ENT2
TDOUT2
TONE
DECODER
TDIN2
OTF
THERMAL
SHUTDOWN
CHARGE PUMP CPSWIN
CPVOUT CPSWOUT
28
29
25
18 9 1 33 35
27 26

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Typical Application Schematic QFN
ISL6422BER

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ISL6422B
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ADDR0/1, CS1/2, EXTM1/2,
SELVTOP1/, TCAP1/2, TDIN1/2, TXT1/2) . . . . . . . . . -0.5V to 7V
Thermal Information
Thermal Resistance (Typical, Notes 2, 3) JA (°C/W) JC (°C/W)
EPTSSOP Package . . . . . . . . . . . . . . .
29
4
QFN Package. . . . . . . . . . . . . . . . . . . .
34
6
Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . -40°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . . -20°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
4. The device junction temperature should be kept below +150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
+150°C typically.
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN1/2 = H,
VTOP1/2 = L, VBOT1/2 = L,
software description section
ENT1/2 = L, DCL = L, MSEL1/2
for I2C access to the system.
=
L,
IOUT
=
12mA,
unless
otherwise
noted.
See
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range
8 12 14
V
Standby Supply Current
EN1 = EN2 = L
-
1.5 3.0
mA
Supply Current
IIN EN1 = EN2 = VTOP1 = VTOP2 = VBOT1 =
VBOT2 = ENT1 = ENT2 = H, No Load
-
4.0 8.0
mA
UNDERVOLTAGE LOCKOUT
Start Threshold
7.50 - 7.97
V
Stop Threshold
7.00 - 7.55
V
Start to Stop Hysteresis
350 400 500
mV
SOFT-START
COMP Rise Time (Note 5)
(Note 5)
- 8196 - Cycles
Output Voltage (Note 5)
Line Regulation
Load Regulation
VO1
VO1
VO1
VO1
VO2
VO2
VO2
VO2
DVO1,
DVO2
DVO1,
DVO2
(Refer to Table 11)
(Refer to Table 11)
(Refer to Table 11)
(Refer to Table 11)
(Refer to Table 15)
(Refer to Table 15)
(Refer to Table 15)
(Refer to Table 15)
VIN = 8V to 14V; VO1, VO2 = 13V
VIN = 8V to 14V; VO1, VO2 = 18V
IO = 12mA to 350mA
IO = 12mA to 750mA (Note 6)
13.04
14.02
17.94
19.00
13.04
14.02
17.94
19.00
-
-
-
-
13.30
14.30
18.30
19.30
13.30
14.30
18.30
19.30
4.0
4.0
50
100
13.56
14.58
18.66
19.68
13.56
14.58
18.66
19.68
40.0
60.0
80
200
V
V
V
V
V
V
V
V
mV
mV
mV
mV
5 FN6486.2
September 8, 2015