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®
Data Sheet
VR11.1 Compatible Synchronous
Rectified Buck MOSFET Drivers
The ISL6620, ISL6620A is a high frequency MOSFET driver
designed to drive upper and lower power N-Channel
MOSFETs in a synchronous rectified buck converter topology.
The advanced PWM protocol of ISL6620, ISL6620A is
specifically designed to work with Intersil VR11.1 controllers
and combined with N-Channel MOSFETs, form a complete
core-voltage regulator solution for advanced microprocessors.
When ISL6620, ISL6620A detects a PSI protocol sent by an
Intersil VR11.1 controller, it activates Diode Emulation (DE)
operation; otherwise, it operates in normal Continuous
Conduction Mode (CCM) PWM mode.
The IC is biased by a single low voltage supply (5V),
minimizing driving losses in high MOSFET gate capacitance
and high switching frequency applications. Each driver is
capable of driving a 3nF load with less than 10ns rise/fall time.
Bootstrapping of the upper gate driver is implemented via an
internal low forward drop diode, reducing implementation cost,
complexity, and allowing the use of higher performance, cost
effective N-Channel MOSFETs.
To further enhance light load efficiency, ISL6620, ISL6620A
enables diode emulation operation during PSI mode. This
allows Discontinuous Conduction Mode (DCM) by detecting
when the inductor current reaches zero and subsequently
turning off the low side MOSFET to prevent it from sinking
current.
An advanced adaptive shoot-through protection is integrated
to prevent both the upper and lower MOSFETs from
conducting simultaneously and to minimize dead time. The
ISL6620, ISL6620A has a 20kΩ integrated high-side
gate-to-source resistor to prevent self turn-on due to high
input bus dV/dt.
ISL6620, ISL6620A
April 25, 2008
FN6494.0
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
• 36V Internal Bootstrap Schottky Diode
• Advanced PWM Protocol (Patent Pending) to Support PSI
Mode, Diode Emulation, Three-State Operation
• Diode Emulation For Enhanced Light Load Efficiency
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency
- 4A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• VCC Undervoltage Protection
• Enable Input and Power-On Reset
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• DFN Package:
- Compliant to JEDEC PUB95 MO-220
DFN - Dual Flat No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and has a Thinner Profile
• Pb-Free (RoHS Compliant)
Applications
• High Light Load Efficiency Voltage Regulators
• Core Regulators for Advanced Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck
Regulators” for Power Train Design, Layout Guidelines,
and Feedback Compensation Design
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6620, ISL6620A
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG. DWG. #
ISL6620CBZ*
6620 CBZ
0 to +70
8 Ld SOIC
M8.15
ISL6620CRZ*
620Z
0 to +70
10 Ld 3x3 DFN
L10.3x3
ISL6620IBZ*
6620 IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL6620IRZ*
620I
-40 to +85
10 Ld 3x3 DFN
L10.3x3
ISL6620ACBZ*
6620A CBZ
0 to +70
8 Ld SOIC
M8.15
ISL6620ACRZ*
620A
0 to +70
10 Ld 3x3 DFN
L10.3x3
ISL6620AIBZ*
6620A IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL6620AIRZ*
20AI
-40 to +85
10 Ld 3x3 DFN
L10.3x3
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Pinouts
ISL6620, ISL6620A
(8 LD SOIC)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 EN
6 VCC
5 LGATE
ISL6620, ISL6620A
(10 LD 3x3 DFN)
TOP VIEW
UGATE 1
BOOT 2
NC 3
PWM 4
5
GND
PAD
10 PHASE
9 EN
8 NC
7 VCC
6 LGATE
Block Diagrams
ISL6620, ISL6620A
VCC
EN
VCC
PWM
4.25k
CONTROL
LOGIC
4k
*RBOOT
SHOOT-
THROUGH
PROTECTION
VCC
BOOT
UGATE
PHASE
LGATE
GND
*INTEGRATED 3Ω RESISTOR (RBOOT) AVAILABLE ONLY IN ISL6620A
2 FN6494.0
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Typical Application Circuit
+5V
VTT
VR_RDY
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI
VR_FAN
VR_HOT
VIN
FB COMP VCC DAC
REF
VDIFF
VSEN
RGND
EN_VTT
PWM1
ISEN1-
ISEN1+
IISSLL66334
PWM2
ISEN2-
ISEN2+
PWM3
ISEN3-
ISEN3+
EN_PWR
GND
IMON
TCOMP
PWM4
ISEN4-
ISEN4+
TM OFS FS SS
+5V +5V
NTC
ISL6620, ISL6620A
+5V
EN
BOOT
VCC
PWM
ISL6620,
ISL6620A
DRIVER
UGATE
PHASE
LGATE
GND
+5V
VCTRL
BOOT
VCC
PWM
ISL6596
DRIVER
UGATE
PHASE
LGATE
GND
+5V
VCTRL
BOOT
VCC
PWM
ISL6596
DRIVER
UGATE
PHASE
LGATE
GND
+5V
VCTRL
BOOT
VCC
PWM
ISL6596
DRIVER
UGATE
PHASE
LGATE
GND
VIN
VIN
VIN
VIN
3
µP
LOAD
FN6494.0
April 25, 2008

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ISL6620, ISL6620A
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . -0.3V to 25V (DC) or 36V (<200ns)
BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC)
GND -8V (<20ns Pulse Width, 10µJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +125°C
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 100
N/A
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range
ISL6620IBZ, ISL6620IRZ, ISL6620AIBZ, ISL6620AIRZ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
ISL6620CBZ, ISL6620CRZ, ISL6620ACBZ, ISL6620ACRZ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC Supply Current
No Load Switching Supply Current
IVCC
f_PWM = 300kHz, V_VCC = 5V
1.27 mA
Standby Supply Current
IVCC
PWM 0V to 2.5V transition, EN = High
1.85
mA
PWM 0V to 2.5V transition, EN = Low
1.15
mA
POWER-ON RESET AND ENABLE
VCC Rising POR Threshold
3.2 3.8
4.4
V
VCC Falling POR Threshold
3.0 3.4
4.0
V
VCC POR Hysteresis
130 300 530 mV
EN High Threshold
1.40 1.65
1.90
V
EN Low Threshold
1.20 1.35
1.55
V
PWM INPUT (See TIMING DIAGRAM" on page 6)
Input Current
IPWM
VPWM = 5V
500 µA
VPWM = 0V
-430
µA
PWM Rising Threshold (Note 4)
VCC = 5V
3.4 V
PWM Falling Threshold (Note 4)
VCC = 5V
1.6 V
Three-State Lower Gate Falling Threshold
VCC = 5V
1.6 V
Three-State Lower Gate Rising Threshold
VCC = 5V
1.1 V
Three-State Upper Gate Rising Threshold
VCC = 5V
3.2 V
Three-state Upper Gate Falling Threshold
VCC = 5V
2.8 V
UGATE Rise Time (Note 4)
t_RU
VCC = 5V, 3nF load, 10% to 90%
8 ns
4 FN6494.0
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ISL6620, ISL6620A
Electrical Specifications
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
LGATE Rise Time (Note 4)
t_RL
VCC = 5V, 3nF load, 10% to 90%
8 ns
UGATE Fall Time (Note 4)
t_FU
VCC = 5V, 3nF load, 10% to 90%
8 ns
LGATE Fall Time (Note 4)
t_FL
VCC = 5V, 3nF load, 10% to 90%
4 ns
UGATE Turn-On Propagation Delay (Note 4) t_PDHU VCC = 5V, 3nF load, adaptive
40 ns
LGATE Turn-On Propagation Delay (Note 4)
t_PDHL VCC = 5V, 3nF load, adaptive
23 ns
UGATE Turn-Off Propagation Delay (Note 4) t_PDLU VCC = 5V, 3nF load
18 ns
LGATE Turn-Off Propagation Delay (Note 4)
t_PDLL VCC = 5V, 3nF load
25 ns
Minimum Lgate on time at Diode emulation t_LG_ON_DM VCC = 5V
230 330 450 ns
OUTPUT (Note 4)
Upper Drive Source Current
I_U_Source VCC = 5V, 3nF load
2A
Upper Drive Source Impedance
R_U_SOURCE 20mA source current
1Ω
Upper Drive Sink Current
I_U_SINK VCC = 5V, 3nF load
2A
Upper Drive Sink Impedance
R_U_SINK 20mA sink current
1Ω
Lower Drive Source Current
I_L_SOURCE VCC = 5V, 3nF load
2A
Lower Drive Source Impedance
R_L_SOURCE 20mA source current
1Ω
Lower Drive Sink Current
I_L_SINK VCC = 5V, 3nF load
4A
Lower Drive Sink Impedance
R_L_SINK 20mA sink current
0.4 Ω
NOTE:
4. Limits should be considered typical and are not production tested.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
- 3, 8 NC No connect.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation.
See “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output
of the controller.
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 VCC Connect this pin to 5V bias supply. This pin supplies power to the upper gate and lower gate drive. Place a high
quality low ESR ceramic capacitor from this pin to GND.
7 9 EN Enable input pin. Connect this pin high to enable driver and low to disable driver.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
- 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
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