ISL644.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 ISL644 데이타시트 다운로드

No Preview Available !

Data Sheet
October 6, 2011
ISL6144
FN9131.7
High Voltage ORing MOSFET Controller
The ISL6144 ORing MOSFET Controller and a suitably sized
N-Channel power MOSFET(s) increases power distribution
efficiency and availability when replacing a power ORing diode
in high current applications.
In a multiple supply, fault tolerant, redundant power distribution
system, paralleled similar power supplies contribute equally to
the load current through various power sharing schemes.
Regardless of the scheme, a common design practice is to
include discrete ORing power diodes to protect against reverse
current flow should one of the power supplies develop a
catastrophic output short to ground. In addition, reverse current
can occur if the current sharing scheme fails and an individual
power supply voltage falls significantly below the others.
Although the discrete ORing diode solution has been used for
some time and is inexpensive to implement, it has some
drawbacks. The primary downside is the increased power
dissipation loss in the ORing diodes as power requirements for
systems increase. Another disadvantage when using an ORing
diode would be failure to detect a shorted or open ORing diode,
jeopardizing power system reliability. An open diode reduces
the system to single point of failure while a diode short might
pose a hazard to technical personnel servicing the system
while unaware of this failure.
The ISL6144 can be used in 9V to 75V systems having similar
power sources and has an internal charge pump to provide a
floating gate drive for the N-Channel ORing MOSFET. The High
Speed (HS) Comparator protects the common bus from
individual power supply shorts by turning off the shorted feed’s
ORing MOSFET in less than 300ns and ensuring low reverse
current.
An external resistor-programmable detection level for the HS
Comparator allows users to set the N-Channel MOSFET
“VOUT - VIN” trip point to adjust control sensitivity to power
supply noise.
The Hysteretic Regulating (HR) Amplifier provides a slow turn-
off of the ORing MOSFET. This turn-off is achieved in less than
100μs when one of the sourcing power supplies is shutdown
slowly for system diagnostics, ensuring zero reverse current.
This slow turn-off mechanism also reacts to output voltage
droop, degradation, or power-down.
An open drain FAULT pin will indicate that a fault has occurred.
The fault detection circuitry covers different types of failures;
including dead short in the sourcing supply, a short of any two
ORing MOSFET terminals, or a blown fuse in the power
distribution path.
Features
• Wide Supply Voltage Range +9V to +75V
• Transient Rating to +100V
• Reverse Current Fault Isolation
• Internal Charge Pump Allows the use of N-Channel
MOSFET
• HS Comparator Provides Very Fast <0.3µs Response
Time to Dead Shorts on Sourcing Supply. HS Comparator
also has Resistor-adjustable Trip Level
• HR Amplifier allows Quiet, <100µs MOSFET Turn-off for
Power Supply Slow Shut Down
• Open Drain, Active Low Fault Output with 120µs Delay
• Provided in Packages Compliant to UL60950 (UL1950)
Creepage Requirements
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free (RoHS Compliant)
Applications
• ORing MOSFET Control in Power Distribution Systems
• N + 1 Redundant Distributed Power Systems
• File and Network Servers (12V and 48V)
• Telecom/Datacom Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
Copyright © Intersil Americas Inc. 2004, 2006-2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

No Preview Available !

ISL6144
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6144IVZA (Note 1)
ISL61 44IVZ
-40 to +105
16 Ld TSSOP
M16.173
ISL6144IRZA (Note 1)
ISL6144 IRZ
-40 to +105
20 Ld 5x5 QFN
L20.5x5
ISL6441EVAL1Z
Evaluation Platform
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6144. For more information on MSL please see techbrief TB363.
Pinouts
ISL6144
(16 LD TSSOP)
TOP VIEW
ISL6144
(20 LD 5x5 QFN)
TOP VIEW
GATE 1
VIN 2
HVREF 3
NC 4
NC 5
NC 6
NC 7
GND 8
16 VOUT
15 COMP
14 VSET
13 NC
12 NC
11 NC
10 NC
9 FAULT
20 19 18 17 16
VIN 1
HVREF 2
NC 3
NC 4
NC 5
15 VOUT
14 COMP
13 VSET
12 NC
11 NC
6 7 8 9 10
Pin Descriptions
TSSOP
PIN #
1
2
3
8
9
14
15
16
4, 5, 6, 7,
10, 11,
12, 13
QFN
PIN #
19
1
2
7
9
SYMBOL
FUNCTION
GATE External FET Gate Drive
VIN Power Supply Connection
HVREF Chip High Voltage Reference
GND Chip Ground Reference
FAULT Fault Output
13
14
15
3, 4, 5, 6, 8,
10, 11, 12,
16, 17,
18, 20
VSET
COMP
VOUT
NC
Low Side Connection for
Trip Level
High Side Connection for HS
Comparator Trip Level
Chip Bias and Load
Connection
No Connection
DESCRIPTION
Allows active control of external N-Channel FET gate to perform ORing function.
Chip bias input. Also provides a sensing node for external FET control.
Low side of floating high voltage reference for all of the HV chip circuitry.
Chip ground reference point.
Provides an open drain active low output as an indication that a fault has
occurred: GATE is OFF (GATE < VIN + 0.37V) or other types of faults
resulting in VIN - VOUT > 0.41V.
Resistor connected to COMP provides adjustable “Vd - Vs” trip level along
with pin COMP.
Resistor connected to VOUT provides sense point for the adjustable Vd - Vs
trip level along with pin VSET.
Provides the second sensing node for external FET control and chip output
bias.
2 FN9131.7
October 6, 2011

No Preview Available !

General Application Circuit
ISL6144
+-
AC/DC
1
VIN GATE VOUT
ISL6144
5V HVREF COMP
FAULTGND VSET
DC/DC
1
VIN GATE VOUT
ISL6144
HVREF
COMP
5V
FAULT
GND
VSET
AC/DC
N+1
VIN GATE VOUT
ISL6144
5V HVREF COMP
FAULTGND VSET
DC/DC
N+1
VIN GATE VOUT
ISL6144
5V HVREF COMP
FAULTGND VSET
NOTES:
4. AC/DC 1 through (N + 1) are multistage AC/DC converters which include AC/DC rectification stage and a DC/DC Converter with a +48VDC
output (also might include a Power Factor Correction stage).
5. DC/DC Converter 1 through (N + 1) are DC/DC converters to provide additional Intermediate Bus.
6. Load “+12V” and Load “+48V” might include other DC/DC converter stages to provide lower voltages such as ±15V, ±5V, +3.3V, +2.5V,
+1.8V etc.
7. Fuse location might vary depending on power system architecture.
FIGURE 1. ISL6144 GENERAL APPLICATION CIRCUIT IN A DISTRIBUTED POWER SYSTEM
3 FN9131.7
October 6, 2011

No Preview Available !

Simplified Block Diagram
SOURCE 2
9V TO 75V
ISL6144
D2*
F2**
SOURCE 1
9V TO 75V
VIN
C1
5.5V
HVREF
FAULT
C1 VIN GATE VOUT R1 C2
HVREF COMP
ISL6144
FAULTGND VSET
D1*
R2
***DF11,,
DF22
PARASITIC DIODES
FUSES COULD ALSO
BE
PLACED
ON THE INPUT SIDE BEFORE THE VIN PIN. THIS
PLACEMENT DEPENDS ON POWER SYSTEM
ARCHITECTURE.
GATE LOGIC AND
CHARGE PUMP
GATE
F1**
VOUT
LOAD
LEVEL
SHIFT
DELAY
100µs
2A* 5mA
FAULT
DETECTION
-
+
REG
AMPLIFIER
-
+
HS
COMP
20mV
-+
HIGH
VOLTAGE
PASS
AND
CLAMPING
5.3V
0.1mA
COMP
VSET
UV
COMP
-
+
0.6V
BIAS
AND
REF
R1 C2
R2
1.5mA
GND
1.5mA
0.2mA
4 FN9131.7
October 6, 2011

No Preview Available !

ISL6144
Absolute Maximum Ratings (Note 8) TA = +25°C
VIN, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +100V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN +12V
HVREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN -5V
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT
VSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT -5V
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
TSSOP Package (Note 9) . . . . . . . . . .
90
N/A
QFN Package (Notes 10, 11) . . . . . . . .
35
5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . +9V to +75V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
8. All voltages are relative to GND, unless otherwise specified.
9. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
10. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
11. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications VIN = 48V, TA = -40°C to +105°C, Unless Otherwise Specified. Boldface limits apply over the operating
temperature range, -40°C to +105°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 12)
TYP
MAX
(Note 12) UNITS
BIAS “VIN
POR Rising
12V Bias Current
48V Bias Current
75V Bias Current
GATE
PORL2H
I12V
I48V
I75V
VIN Rising to VGATE > VIN + 7.5V
VIN = 12V, VGATE = VIN + VGQP
VIN = 48V, VGATE = VIN + VGQP
VIN = 75V, VGATE = VIN + VGQP
8.9 -
- 3.5
- 4.5
-5
-V
- mA
- mA
- mA
Charge Pump Voltage
Gate Low Voltage Level
Low Pull Down Current
High Pull Down Current
Slow Turn-off Time
Fast Turn-off Time
VGQP
VGL
IPDL
IPDH
ttoffs
ttoff
VIN = 12V to 75V
VIN - VOUT < 0V
Cgs = 39nF, IPDL = Cgs*dVgs/Ttofs
Cgs = 39nF, IPDH = Cgs*dVgs/Ttoff
Cgs = 39nF
Turn-off from VGATE = VIN + VGQP to VIN + 1V with
Cgs = 39nF (includes HS Comparator delay time)
VIN + 9
-0.3
-
VIN + 10.5 VIN + 12
VIN VIN + 0.5
5-
-2-
- - 100
- 250 300
V
V
mA
A
µs
ns
Start-up “Turn-On” Time
tON Turn-on from VGATE = VIN to VIN + 7.5V into 39nF
-
1
- ms
GATE Turn-On Current
ION VIN = 9V to 75V
- 1 - mA
CONTROL AND REGULATION I/O
HR Amplifier Forward Voltage
Regulation
HS COMP Externally
Programmable Threshold
VFWD_HR
VTH(HS)
ISL6144 controls voltage across FET Vds to
VFWD_HR during static forward operation at loads
resulting in I * rDS(ON) < VFWD_HR
Externally programmable threshold for noise
sensitivity (system dependent), typical 0.05V to 0.3V
10
0
20
0.05
30 mV
5.3 V
HS Comparator Offset Voltage
Comp Input Current
(Bias Current)
VOS(HS)
ICOMP
-40 0 25 mV
- 1.1 - µA
HVREF Voltage (VIN - HVREF) HVREF(VZ) VIN = 9V to 75V
- 5.5 - V
5 FN9131.7
October 6, 2011