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STB7ANM60N, STD7ANM60N
Datasheet
Automotive-grade N-channel 600 V, 0.8 Ω typ., 5 A MDmesh™ II
Power MOSFETs in D²PAK and DPAK packages
TAB TAB
2
1
D2PAK
3
23
1
DPAK
D(2, TAB)
Features
Order code
STB7ANM60N
STD7ANM60N
VDS
600 V
RDS(on) max.
0.9 Ω
• AEC-Q101 qualified
• 100% avalanche tested
• Low input capacitance and gate charge
• Low gate input resistance
ID
5A
Package
D²PAK
DPAK
G(1)
S(3)
Applications
• Switching applications
AM01475v1_noZen
Description
These devices are N-channel Power MOSFETs developed using the second
generation of MDmesh™ technology. These revolutionary Power MOSFETs
associate a vertical structure to the company’s strip layout to yield one of the world’s
lowest on-resistance and gate charge. They are therefore suitable for the most
demanding high-efficiency converters.
Product status link
STB7ANM60N
STD7ANM60N
Product summary
Order code
STB7ANM60N
Marking
7ANM60N
Package
D²PAK
Packing
Tape and reel
Order code
STD7ANM60N
Marking
7ANM60N
Package
DPAK
Packing
Tape and reel
DS9116 - Rev 3 - November 2018
For further information contact your local STMicroelectronics sales office.
www.st.com

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STB7ANM60N, STD7ANM60N
Electrical ratings
1 Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Parameter
VDS Drain-source voltage
VGS Gate-source voltage
ID Drain current (continuous) at TC = 25 °C
ID Drain current (continuous) at TC = 100 °C
IDM (1)
Drain current (pulsed)
PTOT
Total power dissipation at TC = 25 °C
dv/dt (2)
Peak diode recovery voltage slope
Tj Operating junction temperature range
Tstg Storage temperature range
1. Pulse width limited by safe operating area.
2. ISD ≤ 5 A, di/dt ≤ 400 A/μs, VDSpeak ≤ V(BR)DSS, VDD = 80% V(BR)DSS.
Value
600
±25
5
3
20
45
15
-55 to 150
Table 2. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
Rthj-pcb(1)
Thermal resistance junction-pcb
1. When mounted on 1inch² FR-4 board, 2 oz Cu.
Value
D²PAK
DPAK
2.78
35 50
Symbol
IAS
EAS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive (pulse
width limited by Tjmax)
Single pulse avalanche energy (starting Tj = 25 °C, ID =
IAS, VDD = 50 V)
Value
2
119
Unit
V
V
A
A
A
W
V/ns
°C
Unit
°C/W
°C/W
Unit
A
mJ
DS9116 - Rev 3
page 2/20

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STB7ANM60N, STD7ANM60N
Electrical characteristics
2 Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 4. On/off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
ID = 1 mA, VGS = 0 V
IDSS
IGSS
Zero gate voltage drain
current
Gate body leakage
current
VGS = 0 V, VDS = 600 V
VGS = 0 V, VDS = 600 V, TC = 125 °C (1)
VDS = 0 V, VGS = ±20 V
VGS(th)
RDS(on)
Gate threshold voltage
Static drain-source on
resistance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 2.5 A
1. Defined by design, not subject to production test.
Min.
600
2
Typ.
3
0.8
Max.
1
100
±100
4
0.9
Unit
V
µA
µA
nA
V
Table 5. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Ciss Input capacitance
363
Coss
Crss
Output capacitance
Reverse transfer
capacitance
VDS = 50 V, f = 1 MHz, VGS = 0 V
- 24.6 -
1.1
pF
Coss eq. (1)
Equivalent capacitance
time related
VDS = 0 to 480 V, VGS = 0 V
- 130 -
pF
RG Intrinsic gate resistance f = 1 MHz open drain
- 5.4 -
Ω
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD = 480 V, ID = 5 A, VGS = 0 to 10 V
14
(see Figure 15. Test circuit for gate charge
-
2.7
-
behavior)
7.7
nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.
Symbol
td(on)
tr
td(off)
tf
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
VDD = 300 V, ID = 2.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 14. Test circuit for resistive load
switching times and Figure 19. Switching
time waveform)
Min.
-
Typ.
7
10
26
12
Max.
-
Unit
ns
DS9116 - Rev 3
page 3/20

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STB7ANM60N, STD7ANM60N
Electrical characteristics
Table 7. Source-drain diode
Symbol
Parameter
Test conditions
ISD
ISDM (1)
Source-drain current
Source-drain current
(pulsed)
VSD (2)
trr
Qrr
IRRM
Forward on voltage
ISD = 5 A, VGS = 0 V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 5 A, di/dt = 100 A/µs
VDD = 60 V (see Figure 16. Test circuit for
inductive load switching and diode recovery
times)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 5 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C(see Figure 16. Test
circuit for inductive load switching and
diode recovery times)
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
Min.
-
-
-
-
Typ.
213
1.5
14
265
1.8
14
Max.
5
20
1.3
Unit
A
V
ns
μC
A
ns
μC
A
DS9116 - Rev 3
page 4/20

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STB7ANM60N, STD7ANM60N
Electrical characteristics curves
2.1 Electrical characteristics curves
Figure 1. Safe operating area for D²PAK
ID AM06476v1
10
1
0.1
0.01
0.1
Tj=150°C
Tc=25°C
S ingle
puls e
10µs
100µs
1ms
10ms
1 100 VDS
Figure 3. Safe operating area for DPAK
ID AM06474v1
0
-1
-2
-1
0
Tj=150°C
Tc=25°C
S ingle
puls
2
10µs
100µs
1ms
10ms
DS
Figure 5. Output characterisics
ID(A)
9
8
VG S =1 0 V
AM06477v1
6V
7
6
5
4
5V
3
2
1
0
0 10 20 40 VDS(V)
Figure 2. Thermal impedance for D²PAK
Figure 4. Thermal impedance for DPAK
Figure 6. Transfer characteristics
ID AM06478v1
9 VDS=20V
8
7
6
5
4
3
2
1
0
0 4 8 VGS(V)
DS9116 - Rev 3
page 5/20